From 95e651b9f87f5dc186f4b02e6ae4d15c46497c61 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 29 Sep 2022 15:46:48 -0700 Subject: [PATCH] finish changing to use adde, not addeo for bigint add --- src/openpower/decoder/isa/test_caller_svp64_bigint.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py index d14bf8e1..6f6f6dea 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py @@ -25,9 +25,9 @@ class DecoderTestCase(FHDLTestCase): def test_sv_bigint_add(self): """performs a carry-rollover-vector-add aka "big integer vector add" - this is remarkably simple, each sv.addeo uses and produces a CA which - goes into the next sv.addeo. arbitrary size is possible (1024+) as - is looping using the CA bit from one sv.addeo on another batch to do + this is remarkably simple, each sv.adde uses and produces a CA which + goes into the next sv.adde. arbitrary size is possible (1024+) as + is looping using the CA bit from one sv.adde on another batch to do unlimited-size biginteger add. r3/r2: 0x0000_0000_0000_0001 0xffff_ffff_ffff_ffff + -- 2.30.2