From 95f20a29051ec9065b9a9ea095ee697c4df10175 Mon Sep 17 00:00:00 2001 From: Brad Beckmann Date: Mon, 20 Jul 2015 09:15:20 -0500 Subject: [PATCH] ruby: added stl vector of ints to be used by SLICC --- src/mem/ruby/SConscript | 1 + src/mem/ruby/common/IntVec.cc | 45 ++++++++++++++++++++++++++++++++++ src/mem/ruby/common/IntVec.hh | 41 +++++++++++++++++++++++++++++++ src/mem/ruby/common/SConscript | 1 + 4 files changed, 88 insertions(+) create mode 100644 src/mem/ruby/common/IntVec.cc create mode 100644 src/mem/ruby/common/IntVec.hh diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript index fbbc5686e..3645706db 100644 --- a/src/mem/ruby/SConscript +++ b/src/mem/ruby/SConscript @@ -117,6 +117,7 @@ MakeInclude('slicc_interface/RubyRequest.hh') MakeInclude('common/Address.hh') MakeInclude('common/BoolVec.hh') MakeInclude('common/DataBlock.hh') +MakeInclude('common/IntVec.hh') MakeInclude('common/MachineID.hh') MakeInclude('common/NetDest.hh') MakeInclude('common/Set.hh') diff --git a/src/mem/ruby/common/IntVec.cc b/src/mem/ruby/common/IntVec.cc new file mode 100644 index 000000000..ecd162414 --- /dev/null +++ b/src/mem/ruby/common/IntVec.cc @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015 Advanced Micro Devices, Inc. + * All rights reserved. + * + * For use for simulation and test purposes only + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Brad Beckmann + */ + +#include "mem/ruby/common/IntVec.hh" + +#include +#include + +std::ostream& operator<<(std::ostream& os, const IntVec& myvector) { + for (auto& it : myvector) + os << " " << it; + return os; +} diff --git a/src/mem/ruby/common/IntVec.hh b/src/mem/ruby/common/IntVec.hh new file mode 100644 index 000000000..13e213a88 --- /dev/null +++ b/src/mem/ruby/common/IntVec.hh @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015 Advanced Micro Devices, Inc. + * All rights reserved. + * + * For use for simulation and test purposes only + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Brad Beckmann + */ + +#include +#include + +typedef std::vector IntVec; + +std::ostream& operator<<(std::ostream& os, const std::vector& myvector); diff --git a/src/mem/ruby/common/SConscript b/src/mem/ruby/common/SConscript index 6a53fb7c8..9e809f0d0 100644 --- a/src/mem/ruby/common/SConscript +++ b/src/mem/ruby/common/SConscript @@ -38,5 +38,6 @@ Source('BoolVec.cc') Source('Consumer.cc') Source('DataBlock.cc') Source('Histogram.cc') +Source('IntVec.cc') Source('NetDest.cc') Source('SubBlock.cc') -- 2.30.2