From 95fafa8f05320a761f70bef022a05c3053ea7b27 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 2 Nov 2017 19:15:42 -0700 Subject: [PATCH] Mask medeleg correctly --- riscv/processor.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 203394b..d23c1ea 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -360,9 +360,13 @@ void processor_t::set_csr(int which, reg_t val) state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints); break; case CSR_MEDELEG: { - reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT - | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT - | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT; + reg_t mask = + (1 << CAUSE_MISALIGNED_FETCH) | + (1 << CAUSE_BREAKPOINT) | + (1 << CAUSE_USER_ECALL) | + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT); state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } -- 2.30.2