From 95fcf66fa63689d6b3a5a8a5e01fd6741928def0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Nov 2021 14:53:04 +0000 Subject: [PATCH] add RT as an option for ternary instruction as 3rd register input --- src/openpower/decoder/power_decoder2.py | 4 ++++ src/openpower/decoder/power_enums.py | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index edf2893b..7dc213d6 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -362,6 +362,10 @@ class DecodeC(Elaboratable): with m.Case(In3Sel.RC): comb += reg.data.eq(self.dec.RC) comb += reg.ok.eq(1) + with m.Case(In3Sel.RT): + # for TII-form ternary + comb += reg.data.eq(self.dec.RT) + comb += reg.ok.eq(1) return m diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index ec9ed77d..5757fb6d 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -478,7 +478,8 @@ class In3Sel(Enum): FRS = 3 FRC = 4 RC = 5 # for SVP64 bit-reverse LD/ST - CONST_TII = 6 # for ternaryi + CONST_TII = 6 # for ternaryi - XXX TODO: REMOVE THIS (from CSV, first) + RT = 7 # for ternary @unique -- 2.30.2