From 962dce9a0a139a516907f4a9bd640f60b6279440 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 21 Jun 2022 20:42:02 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 303356e25..4283e0769 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -43,9 +43,8 @@ The Mode table for Arithmetic and Logical operations | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | | 00 | 0 | dz sz | normal mode | -| 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | -| 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | -| 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | +| 00 | 1 | 0 RG | scalar reduce mode (mapreduce) | +| 00 | 1 | 1 / | parallel reduce mode (mapreduce) | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz | | 10 | N | dz sz | sat mode: N=0/1 u/s | @@ -59,7 +58,6 @@ Fields: * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) * **RG** inverts the Vector Loop order (VL-1 downto 0) rather than the normal 0..VL-1 -* **SVM** sets "subvector" reduce mode * **N** sets signed/unsigned saturation. * **RC1** as if Rc=1, stores CRs *but not the result* * **VLi** VL inclusive: in fail-first mode, the truncation of -- 2.30.2