From 96372419e33a6a3ef728e6502315a7302b8fe8b6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Jun 2020 22:38:37 +0100 Subject: [PATCH] need args to WishboneArbiter, match data width size --- src/soc/minerva/units/fetch.py | 26 ++++++++++++++------------ src/soc/minerva/units/loadstore.py | 9 +++++---- src/soc/minerva/wishbone.py | 4 ++-- 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index dd691aeb..6b78e801 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -107,22 +107,24 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable): icache.s2_valid.eq(self.f_valid_i & f_icache_select) ] - ibus_arbiter = m.submodules.ibus_arbiter = WishboneArbiter() - m.d.comb += ibus_arbiter.bus.connect(self.ibus) + iba = WishboneArbiter(self.addr_wid, self.adr_lsbs, self.data_wid) + m.submodules.ibus_arbiter = iba + m.d.comb += iba.bus.connect(self.ibus) - icache_pt = ibus_arbiter.port(priority=0) + icache_port = iba.port(priority=0) + cti = Mux(icache.bus_last, Cycle.END, Cycle.INCREMENT m.d.comb += [ - icache_pt.cyc.eq(icache.bus_re), - icache_pt.stb.eq(icache.bus_re), - icache_pt.adr.eq(icache.bus_addr), - icache_pt.cti.eq(Mux(icache.bus_last, Cycle.END, Cycle.INCREMENT)), - icache_pt.bte.eq(Const(log2_int(icache.nwords) - 1)), - icache.bus_valid.eq(icache_pt.ack), - icache.bus_error.eq(icache_pt.err), - icache.bus_rdata.eq(icache_pt.dat_r) + icache_port.cyc.eq(icache.bus_re), + icache_port.stb.eq(icache.bus_re), + icache_port.adr.eq(icache.bus_addr), + icache_port.cti.eq(cti), + icache_port.bte.eq(Const(log2_int(icache.nwords) - 1)), + icache.bus_valid.eq(icache_port.ack), + icache.bus_error.eq(icache_port.err), + icache.bus_rdata.eq(icache_port.dat_r) ] - bare_port = ibus_arbiter.port(priority=1) + bare_port = iba.port(priority=1) bare_rdata = Signal.like(bare_port.dat_r) with m.If(bare_port.cyc): with m.If(bare_port.ack | bare_port.err | ~self.f_valid_i): diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index ec80dd6d..e9a35609 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -155,8 +155,9 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): wrbuf_r_data.eq(wrbuf.r_data), ] - dbus_arbiter = m.submodules.dbus_arbiter = WishboneArbiter() - m.d.comb += dbus_arbiter.bus.connect(self.dbus) + dba = WishboneArbiter(self.addr_wid, self.mask_wid, self.data_wid) + m.submodules.dbus_arbiter = dba + m.d.comb += dba.bus.connect(self.dbus) wrbuf_port = dbus_arbiter.port(priority=0) with m.If(wrbuf_port.cyc): @@ -176,7 +177,7 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): ] m.d.comb += wrbuf_port.we.eq(Const(1)) - dcache_port = dbus_arbiter.port(priority=1) + dcache_port = dba.port(priority=1) cti = Mux(dcache.bus_last, Cycle.END, Cycle.INCREMENT) m.d.comb += [ dcache_port.cyc.eq(dcache.bus_re), @@ -189,7 +190,7 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): dcache.bus_rdata.eq(dcache_port.dat_r) ] - bare_port = dbus_arbiter.port(priority=2) + bare_port = dba.port(priority=2) bare_rdata = Signal.like(bare_port.dat_r) with m.If(bare_port.cyc): with m.If(bare_port.ack | bare_port.err | ~self.m_valid_i): diff --git a/src/soc/minerva/wishbone.py b/src/soc/minerva/wishbone.py index 1f56619f..27176786 100644 --- a/src/soc/minerva/wishbone.py +++ b/src/soc/minerva/wishbone.py @@ -36,8 +36,8 @@ wishbone_layout = make_wb_layout(32, 4, 32) class WishboneArbiter(Elaboratable): - def __init__(self): - self.bus = Record(wishbone_layout) + def __init__(self, addr_wid=32, mask_wid=4, data_wid=32): + self.bus = Record(make_wb_layout(addr_wid, mask_wid, data_wid)) self._port_map = dict() def port(self, priority): -- 2.30.2