From 967297cd57f80f0b55f7e1d1e00fd6c20b8fb52a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 Feb 2019 18:40:53 -0800 Subject: [PATCH] abc9 cleanup --- passes/techmap/abc9.cc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 68e54f518..de47de92e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -892,21 +892,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } log_assert(GetSize(signal) >= GetSize(remap_wire)); + log_assert(w->port_input || w->port_output); + RTLIL::SigSig conn; if (w->port_input) { - RTLIL::SigSig conn; conn.first = remap_wire; conn.second = signal; in_wires++; - module->connect(conn); } - else if (w->port_output) { - RTLIL::SigSig conn; + if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; - module->connect(conn); } - else log_abort(); + module->connect(conn); } //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); -- 2.30.2