From 96b92eb50b05be9423cb80ebacae64cc4f3a81c7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jun 2020 14:35:23 +0100 Subject: [PATCH] whoops forgot to call parent elaborate --- src/soc/bus/test/test_minerva.py | 2 +- src/soc/config/test/test_loadstore.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py index eeb4a955..299c9379 100644 --- a/src/soc/bus/test/test_minerva.py +++ b/src/soc/bus/test/test_minerva.py @@ -8,7 +8,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): super().__init__(addr_wid, mask_wid, data_wid) def elaborate(self, platform): - m = Module() + m = super().elaborate(platform) comb = m.d.comb # small 32-entry Memory memory = Memory(width=self.addr_wid, depth=32) diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py index e9bf98a8..783fe002 100644 --- a/src/soc/config/test/test_loadstore.py +++ b/src/soc/config/test/test_loadstore.py @@ -86,8 +86,8 @@ def tst_lsmemtype(ifacetype): for addr, val in enumerate(values): yield from write_to_addr(dut, addr << 2, val) - for addr, val in enumerate(values): x = yield from read_from_addr(dut, addr << 2) + print ("addr, val", addr, val, x) assert x == val values = [random.randint(0, 255) for x in range(16*4)] -- 2.30.2