From 96bb360b5b2de83f6913a156317014fcb3fa6e05 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 11 Jun 2020 06:11:29 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/memory_and_cache.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index a9f0910f9..e3ad496b5 100644
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -39,7 +39,7 @@ Basic diagram:
   [Enjoy-Digital Litex](https://github.com/enjoy-digital/litex)
   code takes over, and connect to peripherals and testing infrastructure.
 
-* Memory is the silicon-proven OpenCores [SDRAM|sdram] interface,
+* Memory is the silicon-proven OpenCores [[SDRAM|sdram]] interface,
   and it is Wishbone compliant.
 
 ## Memory Interface Required by LDSTComputationalUnit
-- 
2.30.2