From 96c2f5441e58e5b24911633498f22ce1551b8941 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 10 May 2023 14:17:24 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls012.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index 9cf93f38d..1aa504f6d 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -272,6 +272,17 @@ area of research on its own deemed unlikely to be achievable. Note: none of these instructions are in VSX. They are a different paradigm and have more akin with their x86 equivalents. +**Critical to note regarding 2-out instructions**: + + + +``` +>For example, having instructions with 2 dest registers changes +>the cost for a multi-lane OoO renamer from BigO(n^2) to BigO((2n)^2) +>so a 4-lane 2-dest renamer costs 16 times as much. +>And this is for a feature that would be rarely used and is redundant. +``` + ## fclass and GPR-FPR moves [[sv/fclass]] - just one instruction. With SFFS being locked down to -- 2.30.2