From 96dc900e690e68e465b0ef92455935d6bb6bf8a3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Apr 2022 16:38:54 +0100 Subject: [PATCH] add default args in DDR3SoC --- src/ls2.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 61be6fb..e046a49 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -237,14 +237,14 @@ class WB64to32Convert(Elaboratable): class DDR3SoC(SoC, Elaboratable): def __init__(self, *, fpga, - dram_cls, - uart_pins, spi_0_pins, ethmac_0_pins, - ddr_pins, ddrphy_addr, dramcore_addr, ddr_addr, - fw_addr=0x0000_0000, - firmware=None, - uart_addr=None, uart_irqno, - spi0_addr, spi0_cfg_addr, - eth0_cfg_addr, eth0_irqno, + dram_cls=None, + uart_pins=None, spi_0_pins=None, ethmac_0_pins=None, + ddr_pins=None, ddrphy_addr=None, + dramcore_addr=None, ddr_addr=None, + fw_addr=0x0000_0000, firmware=None, + uart_addr=None, uart_irqno=0, + spi0_addr=None, spi0_cfg_addr=None, + eth0_cfg_addr=None, eth0_irqno=None, hyperram_addr=None, hyperram_pins=None, xics_icp_addr=None, xics_ics_addr=None, -- 2.30.2