From 96ddc2959d8ce96bf88cd53d7f9353add52fdedf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 18:48:46 +0100 Subject: [PATCH] comment clarify on core --- src/soc/simple/test/test_core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 68357ac2..da844e34 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -146,11 +146,11 @@ class TestRunner(FHDLTestCase): gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) - # set up INT regfile, "direct" write from sim data + # set up INT regfile, "direct" write (bypass rd/write ports) for i in range(32): yield core.regs.int.regs[i].reg.eq(test.regs[i]) - # set up XER + # set up XER. "direct" write (bypass rd/write ports) xregs = core.regs.xer print ("sprs", test.sprs) if special_sprs['XER'] in test.sprs: -- 2.30.2