From 96f01501d7a5f5242cba8641a2f20e965ce3aa94 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 4 May 2018 22:46:49 -0700 Subject: [PATCH] i965: Move brw_emit_depth_stencil_hiz higher up in the file Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_misc_state.c | 90 ++++++++++------------ 1 file changed, 40 insertions(+), 50 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e44baf25185..03535f689ea 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -262,7 +262,46 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, struct intel_mipmap_tree *stencil_mt, bool hiz, bool separate_stencil, uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); + uint32_t tile_x, uint32_t tile_y) +{ + (void)hiz; + (void)separate_stencil; + (void)stencil_mt; + + assert(!hiz); + assert(!separate_stencil); + + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5; + + BEGIN_BATCH(len); + OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); + OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | + (depthbuffer_format << 18) | + (BRW_TILEWALK_YMAJOR << 26) | + (1 << 27) | + (depth_surface_type << 29)); + + if (depth_mt) { + OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset); + } else { + OUT_BATCH(0); + } + + OUT_BATCH(((width + tile_x - 1) << 6) | + ((height + tile_y - 1) << 19)); + OUT_BATCH(0); + + if (devinfo->is_g4x || devinfo->gen >= 5) + OUT_BATCH(tile_x | (tile_y << 16)); + else + assert(tile_x == 0 && tile_y == 0); + + if (devinfo->gen >= 6) + OUT_BATCH(0); + + ADVANCE_BATCH(); +} void brw_emit_depthbuffer(struct brw_context *brw) @@ -469,55 +508,6 @@ brw_emit_depthbuffer(struct brw_context *brw) brw->no_depth_or_stencil = !depth_mt && !stencil_mt; } -static void -brw_emit_depth_stencil_hiz(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y) -{ - (void)hiz; - (void)separate_stencil; - (void)stencil_mt; - - assert(!hiz); - assert(!separate_stencil); - - const struct gen_device_info *devinfo = &brw->screen->devinfo; - const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5; - - BEGIN_BATCH(len); - OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); - OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | - (depthbuffer_format << 18) | - (BRW_TILEWALK_YMAJOR << 26) | - (1 << 27) | - (depth_surface_type << 29)); - - if (depth_mt) { - OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset); - } else { - OUT_BATCH(0); - } - - OUT_BATCH(((width + tile_x - 1) << 6) | - ((height + tile_y - 1) << 19)); - OUT_BATCH(0); - - if (devinfo->is_g4x || devinfo->gen >= 5) - OUT_BATCH(tile_x | (tile_y << 16)); - else - assert(tile_x == 0 && tile_y == 0); - - if (devinfo->gen >= 6) - OUT_BATCH(0); - - ADVANCE_BATCH(); -} - const struct brw_tracked_state brw_depthbuffer = { .dirty = { .mesa = _NEW_BUFFERS, -- 2.30.2