From 96f482fd6cc01f9181360daac0ae80e2dee40401 Mon Sep 17 00:00:00 2001 From: Ian Jiang Date: Fri, 14 Aug 2020 10:13:41 +0800 Subject: [PATCH] arch-riscv: Fix disassembling of all register instructions How many Rs to output in disassembling register instructions? It does not depend on wheather the register index is zero, but on the count of source registers. This patch fixes the problem. Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86 Signed-off-by: Ian Jiang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/riscv/insts/standard.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index e6c2b67ae..9a9aa9da4 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -48,9 +48,9 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << registerName(_srcRegIdx[0]); - if (_srcRegIdx[1].index() != 0) + if (_numSrcRegs >= 2) ss << ", " << registerName(_srcRegIdx[1]); - if (_srcRegIdx[2].index() != 0) + if (_numSrcRegs >= 3) ss << ", " << registerName(_srcRegIdx[2]); return ss.str(); } -- 2.30.2