From 96feaf79b2285aca415fda727e51868b95a8e4d9 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Wed, 7 Jun 2017 01:55:12 +0000 Subject: [PATCH] Remove aarch32 support for falkor/qdf24xx, not in released hardware. gcc/ * config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs): Move to here. * config/arm/aarch-cost-tables.h (qdf24xx_extra_costs): From here. * config/arm/arm-cpu-cdata.h: Regenerate. * config/arm/arm-cpu-data.h, config/arm/arm-cpu.h: Likewise. * config/arm/arm-tables.opt, config/arm/arm-tune.md: Likewise. * config/arm/arm-cpus.in: Delete falkor and qdf24xx entries. * config/arm/arm.c (arm_qdf24xx_tune): Delete. * config/arm/bpabi.h (BE8_LINK_SPEC): Delete falkor and qdf24xx support. * config/arm/t-aprofile (MULTILIB_MATCHES): Delete falkor and qdf24xx support. * config/arm/t-rmprofile: Likewise. * doc/invoke.texi (ARM Options): Drop falkor and qdf24xx support. From-SVN: r248944 --- gcc/ChangeLog | 17 ++++ gcc/config/aarch64/aarch64-cost-tables.h | 108 ++++++++++++++++++++++- gcc/config/arm/aarch-cost-tables.h | 103 --------------------- gcc/config/arm/arm-cpu-cdata.h | 14 --- gcc/config/arm/arm-cpu-data.h | 22 ----- gcc/config/arm/arm-cpu.h | 2 - gcc/config/arm/arm-cpus.in | 14 --- gcc/config/arm/arm-tables.opt | 6 -- gcc/config/arm/arm-tune.md | 7 +- gcc/config/arm/arm.c | 22 ----- gcc/config/arm/bpabi.h | 4 - gcc/config/arm/t-aprofile | 2 - gcc/config/arm/t-rmprofile | 1 - gcc/doc/invoke.texi | 4 +- 14 files changed, 127 insertions(+), 199 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a394bcbb1f0..519fd625851 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2017-06-06 Jim Wilson + + * config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs): Move to + here. + * config/arm/aarch-cost-tables.h (qdf24xx_extra_costs): From here. + * config/arm/arm-cpu-cdata.h: Regenerate. + * config/arm/arm-cpu-data.h, config/arm/arm-cpu.h: Likewise. + * config/arm/arm-tables.opt, config/arm/arm-tune.md: Likewise. + * config/arm/arm-cpus.in: Delete falkor and qdf24xx entries. + * config/arm/arm.c (arm_qdf24xx_tune): Delete. + * config/arm/bpabi.h (BE8_LINK_SPEC): Delete falkor and qdf24xx + support. + * config/arm/t-aprofile (MULTILIB_MATCHES): Delete falkor and qdf24xx + support. + * config/arm/t-rmprofile: Likewise. + * doc/invoke.texi (ARM Options): Drop falkor and qdf24xx support. + 2017-06-06 David S. Miller PR target/80968 diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h index bde1f10058b..070c083beb3 100644 --- a/gcc/config/aarch64/aarch64-cost-tables.h +++ b/gcc/config/aarch64/aarch64-cost-tables.h @@ -23,7 +23,111 @@ #include "config/arm/aarch-cost-tables.h" -/* ThunderX does not have implement AArch32. */ +/* QDF24xx does not implement AArch32. */ +const struct cpu_cost_table qdf24xx_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + 0, /* shift. */ + 0, /* shift_reg. */ + COSTS_N_INSNS (1), /* arith_shift. */ + COSTS_N_INSNS (1), /* arith_shift_reg. */ + 0, /* log_shift. */ + 0, /* log_shift_reg. */ + 0, /* extend. */ + 0, /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* rev. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (2), /* simple. */ + COSTS_N_INSNS (2), /* flag_setting. */ + COSTS_N_INSNS (2), /* extend. */ + COSTS_N_INSNS (2), /* add. */ + COSTS_N_INSNS (2), /* extend_add. */ + COSTS_N_INSNS (4) /* idiv. */ + }, + /* MULT DImode */ + { + COSTS_N_INSNS (3), /* simple. */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (3), /* extend. */ + COSTS_N_INSNS (3), /* add. */ + COSTS_N_INSNS (3), /* extend_add. */ + COSTS_N_INSNS (9) /* idiv. */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (2), /* load. */ + COSTS_N_INSNS (2), /* load_sign_extend. */ + COSTS_N_INSNS (2), /* ldrd. */ + COSTS_N_INSNS (2), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 2, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (2), /* loadf. */ + COSTS_N_INSNS (2), /* loadd. */ + COSTS_N_INSNS (3), /* load_unaligned. */ + 0, /* store. */ + 0, /* strd. */ + 0, /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 2, /* stm_regs_per_insn_subsequent. */ + 0, /* storef. */ + 0, /* stored. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (6), /* div. */ + COSTS_N_INSNS (5), /* mult. */ + COSTS_N_INSNS (5), /* mult_addsub. */ + COSTS_N_INSNS (5), /* fma. */ + COSTS_N_INSNS (3), /* addsub. */ + COSTS_N_INSNS (1), /* fpconst. */ + COSTS_N_INSNS (1), /* neg. */ + COSTS_N_INSNS (2), /* compare. */ + COSTS_N_INSNS (4), /* widen. */ + COSTS_N_INSNS (4), /* narrow. */ + COSTS_N_INSNS (4), /* toint. */ + COSTS_N_INSNS (4), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (11), /* div. */ + COSTS_N_INSNS (6), /* mult. */ + COSTS_N_INSNS (6), /* mult_addsub. */ + COSTS_N_INSNS (6), /* fma. */ + COSTS_N_INSNS (3), /* addsub. */ + COSTS_N_INSNS (1), /* fpconst. */ + COSTS_N_INSNS (1), /* neg. */ + COSTS_N_INSNS (2), /* compare. */ + COSTS_N_INSNS (4), /* widen. */ + COSTS_N_INSNS (4), /* narrow. */ + COSTS_N_INSNS (4), /* toint. */ + COSTS_N_INSNS (4), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* alu. */ + } +}; + +/* ThunderX does not implement AArch32. */ const struct cpu_cost_table thunderx_extra_costs = { /* ALU */ @@ -230,6 +334,4 @@ const struct cpu_cost_table thunderx2t99_extra_costs = } }; - #endif - diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 68f84b04fe2..da8ca1b989c 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -537,107 +537,4 @@ const struct cpu_cost_table xgene1_extra_costs = } }; -const struct cpu_cost_table qdf24xx_extra_costs = -{ - /* ALU */ - { - 0, /* arith. */ - 0, /* logical. */ - 0, /* shift. */ - 0, /* shift_reg. */ - COSTS_N_INSNS (1), /* arith_shift. */ - COSTS_N_INSNS (1), /* arith_shift_reg. */ - 0, /* log_shift. */ - 0, /* log_shift_reg. */ - 0, /* extend. */ - 0, /* extend_arith. */ - 0, /* bfi. */ - 0, /* bfx. */ - 0, /* clz. */ - 0, /* rev. */ - 0, /* non_exec. */ - true /* non_exec_costs_exec. */ - }, - { - /* MULT SImode */ - { - COSTS_N_INSNS (2), /* simple. */ - COSTS_N_INSNS (2), /* flag_setting. */ - COSTS_N_INSNS (2), /* extend. */ - COSTS_N_INSNS (2), /* add. */ - COSTS_N_INSNS (2), /* extend_add. */ - COSTS_N_INSNS (4) /* idiv. */ - }, - /* MULT DImode */ - { - COSTS_N_INSNS (3), /* simple. */ - 0, /* flag_setting (N/A). */ - COSTS_N_INSNS (3), /* extend. */ - COSTS_N_INSNS (3), /* add. */ - COSTS_N_INSNS (3), /* extend_add. */ - COSTS_N_INSNS (9) /* idiv. */ - } - }, - /* LD/ST */ - { - COSTS_N_INSNS (2), /* load. */ - COSTS_N_INSNS (2), /* load_sign_extend. */ - COSTS_N_INSNS (2), /* ldrd. */ - COSTS_N_INSNS (2), /* ldm_1st. */ - 1, /* ldm_regs_per_insn_1st. */ - 2, /* ldm_regs_per_insn_subsequent. */ - COSTS_N_INSNS (2), /* loadf. */ - COSTS_N_INSNS (2), /* loadd. */ - COSTS_N_INSNS (3), /* load_unaligned. */ - 0, /* store. */ - 0, /* strd. */ - 0, /* stm_1st. */ - 1, /* stm_regs_per_insn_1st. */ - 2, /* stm_regs_per_insn_subsequent. */ - 0, /* storef. */ - 0, /* stored. */ - COSTS_N_INSNS (1), /* store_unaligned. */ - COSTS_N_INSNS (1), /* loadv. */ - COSTS_N_INSNS (1) /* storev. */ - }, - { - /* FP SFmode */ - { - COSTS_N_INSNS (6), /* div. */ - COSTS_N_INSNS (5), /* mult. */ - COSTS_N_INSNS (5), /* mult_addsub. */ - COSTS_N_INSNS (5), /* fma. */ - COSTS_N_INSNS (3), /* addsub. */ - COSTS_N_INSNS (1), /* fpconst. */ - COSTS_N_INSNS (1), /* neg. */ - COSTS_N_INSNS (2), /* compare. */ - COSTS_N_INSNS (4), /* widen. */ - COSTS_N_INSNS (4), /* narrow. */ - COSTS_N_INSNS (4), /* toint. */ - COSTS_N_INSNS (4), /* fromint. */ - COSTS_N_INSNS (2) /* roundint. */ - }, - /* FP DFmode */ - { - COSTS_N_INSNS (11), /* div. */ - COSTS_N_INSNS (6), /* mult. */ - COSTS_N_INSNS (6), /* mult_addsub. */ - COSTS_N_INSNS (6), /* fma. */ - COSTS_N_INSNS (3), /* addsub. */ - COSTS_N_INSNS (1), /* fpconst. */ - COSTS_N_INSNS (1), /* neg. */ - COSTS_N_INSNS (2), /* compare. */ - COSTS_N_INSNS (4), /* widen. */ - COSTS_N_INSNS (4), /* narrow. */ - COSTS_N_INSNS (4), /* toint. */ - COSTS_N_INSNS (4), /* fromint. */ - COSTS_N_INSNS (2) /* roundint. */ - } - }, - /* Vector */ - { - COSTS_N_INSNS (1) /* alu. */ - } -}; - #endif /* GCC_AARCH_COST_TABLES_H */ diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index b3888120daa..b00d83302f6 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -739,20 +739,6 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = isa_nobit }, }, - { - "falkor", - { - ISA_ARMv8a,isa_bit_crc32, - isa_nobit - }, - }, - { - "qdf24xx", - { - ISA_ARMv8a,isa_bit_crc32, - isa_nobit - }, - }, { "xgene1", { diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 8d47e7c7492..78421adb9e5 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -1143,28 +1143,6 @@ static const struct processors all_cores[] = }, &arm_exynosm1_tune }, - { - "falkor", - TARGET_CPU_cortexa57, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a,isa_bit_crc32, - isa_nobit - }, - &arm_qdf24xx_tune - }, - { - "qdf24xx", - TARGET_CPU_cortexa57, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a,isa_bit_crc32, - isa_nobit - }, - &arm_qdf24xx_tune - }, { "xgene1", TARGET_CPU_xgene1, diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h index cd282db02f5..cc0cb0017eb 100644 --- a/gcc/config/arm/arm-cpu.h +++ b/gcc/config/arm/arm-cpu.h @@ -123,8 +123,6 @@ enum processor_type TARGET_CPU_cortexa72, TARGET_CPU_cortexa73, TARGET_CPU_exynosm1, - TARGET_CPU_falkor, - TARGET_CPU_qdf24xx, TARGET_CPU_xgene1, TARGET_CPU_cortexa57cortexa53, TARGET_CPU_cortexa72cortexa53, diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index d116b09eabb..1100f3a5411 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1020,20 +1020,6 @@ begin cpu exynos-m1 costs exynosm1 end cpu exynos-m1 -begin cpu falkor - tune for cortex-a57 - tune flags LDSCHED - architecture armv8-a+crc - costs qdf24xx -end cpu falkor - -begin cpu qdf24xx - tune for cortex-a57 - tune flags LDSCHED - architecture armv8-a+crc - costs qdf24xx -end cpu qdf24xx - begin cpu xgene1 tune flags LDSCHED architecture armv8-a diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index cbcd85d9906..cb45e097c90 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -327,12 +327,6 @@ Enum(processor_type) String(cortex-a73) Value( TARGET_CPU_cortexa73) EnumValue Enum(processor_type) String(exynos-m1) Value( TARGET_CPU_exynosm1) -EnumValue -Enum(processor_type) String(falkor) Value( TARGET_CPU_falkor) - -EnumValue -Enum(processor_type) String(qdf24xx) Value( TARGET_CPU_qdf24xx) - EnumValue Enum(processor_type) String(xgene1) Value( TARGET_CPU_xgene1) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 13db413459f..6252d42d4d8 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -54,8 +54,7 @@ cortexm3,marvell_pj4,cortexa15cortexa7, cortexa17cortexa7,cortexa32,cortexa35, cortexa53,cortexa57,cortexa72, - cortexa73,exynosm1,falkor, - qdf24xx,xgene1,cortexa57cortexa53, - cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53, - cortexm23,cortexm33" + cortexa73,exynosm1,xgene1, + cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, + cortexa73cortexa53,cortexm23,cortexm33" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 42b0e867a18..2604102c202 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2094,28 +2094,6 @@ const struct tune_params arm_xgene1_tune = tune_params::SCHED_AUTOPREF_OFF }; -const struct tune_params arm_qdf24xx_tune = -{ - &qdf24xx_extra_costs, - NULL, /* Scheduler cost adjustment. */ - arm_default_branch_cost, - &arm_default_vec_cost, /* Vectorizer costs. */ - 1, /* Constant limit. */ - 2, /* Max cond insns. */ - 8, /* Memset max inline. */ - 4, /* Issue rate. */ - ARM_PREFETCH_BENEFICIAL (0, -1, 64), - tune_params::PREF_CONST_POOL_FALSE, - tune_params::PREF_LDRD_TRUE, - tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */ - tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */ - tune_params::DISPARAGE_FLAGS_ALL, - tune_params::PREF_NEON_64_FALSE, - tune_params::PREF_NEON_STRINGOPS_TRUE, - FUSE_OPS (tune_params::FUSE_MOVW_MOVT), - tune_params::SCHED_AUTOPREF_FULL -}; - /* Branches can be dual-issued on Cortex-A5, so conditional execution is less appealing. Set max_insns_skipped to a low value. */ diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index 56a4a475042..f9f9a9248d4 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -79,8 +79,6 @@ |mcpu=cortex-a73.cortex-a35 \ |mcpu=cortex-a73.cortex-a53 \ |mcpu=exynos-m1 \ - |mcpu=falkor \ - |mcpu=qdf24xx \ |mcpu=xgene1 \ |mcpu=cortex-m1.small-multiply \ |mcpu=cortex-m0.small-multiply \ @@ -118,8 +116,6 @@ |mcpu=cortex-a73.cortex-a35 \ |mcpu=cortex-a73.cortex-a53 \ |mcpu=exynos-m1 \ - |mcpu=falkor \ - |mcpu=qdf24xx \ |mcpu=xgene1 \ |mcpu=cortex-m1.small-multiply \ |mcpu=cortex-m0.small-multiply \ diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index b71cbda3e81..10e2d34062d 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -79,8 +79,6 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1 -MULTILIB_MATCHES += march?armv8-a=mcpu?falkor -MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1 # Arch Matches diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index 8cd735110b6..ee869b761f7 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -112,7 +112,6 @@ MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73 MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a35 MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a53 MULTILIB_MATCHES += march?armv7=mcpu?exynos-m1 -MULTILIB_MATCHES += march?armv7=mcpu?qdf24xx MULTILIB_MATCHES += march?armv7=mcpu?xgene1 # Arch Matches diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4a83a3e39eb..456fa85d40a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14058,8 +14058,8 @@ processors implementing the target architecture. Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor}, -@samp{qdf24xx}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, +@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, +@samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, -- 2.30.2