From 97160c9b3b6e524efd7ee4e12dfcd82519d27246 Mon Sep 17 00:00:00 2001 From: Dominik Vogt Date: Tue, 25 Apr 2017 07:33:05 +0000 Subject: [PATCH] S/390: Load and test peephole. gcc/ChangeLog: 2017-04-25 Dominik Vogt * config/s390/s390.md (define_peephole2): New peephole to help combining the load-and-test pattern with volatile memory. From-SVN: r247131 --- gcc/ChangeLog | 5 +++++ gcc/config/s390/s390.md | 15 +++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2f2365b0b18..7106442a8c4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-04-25 Dominik Vogt + + * config/s390/s390.md (define_peephole2): New peephole to help + combining the load-and-test pattern with volatile memory. + 2017-04-25 Dominik Vogt * config/s390/s390.md ("cstorecc4"): Use load-on-condition and deal diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 6a1cab6947a..9baafccdf5a 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -907,6 +907,21 @@ [(set_attr "op_type" "RR,RXY") (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) +; Peephole to combine a load-and-test from volatile memory which combine does +; not do. +(define_peephole2 + [(set (match_operand:GPR 0 "register_operand") + (match_operand:GPR 2 "memory_operand")) + (set (reg CC_REGNUM) + (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] + "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM + && GENERAL_REG_P (operands[0]) + && satisfies_constraint_T (operands[2])" + [(parallel + [(set (reg:CCS CC_REGNUM) + (compare:CCS (match_dup 2) (match_dup 1))) + (set (match_dup 0) (match_dup 2))])]) + ; ltr, lt, ltgr, ltg (define_insn "*tst_cconly_extimm" [(set (reg CC_REGNUM) -- 2.30.2