From 9722215a027b68651c3c7a8af9204d033197e9c0 Mon Sep 17 00:00:00 2001 From: Mihail Ionescu Date: Wed, 15 Jan 2020 10:38:44 +0000 Subject: [PATCH] [PATCH, GCC/ARM, 4/10] Clear GPR with CLRM This patch adds a new pattern for the CLRM instruction and guards the current clearing code in output_return_instruction() and thumb_exit() on Armv8.1-M Mainline instructions not being present. cmse_clear_registers () is then modified to use the new CLRM instruction when targeting Armv8.1-M Mainline while keeping Armv8-M register clearing code for VFP registers. For the CLRM instruction, which does not mandated APSR in the register list, checking whether it is the right volatile unspec or a clearing register is done in clear_operation_p. Note that load/store multiple were deemed sufficiently different in terms of RTX structure compared to the CLRM pattern for a different function to be used to validate the match_parallel. ChangeLog entries are as follows: *** gcc/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu 2020-01-16 Thomas Preud'homme * config/arm/arm-protos.h (clear_operation_p): Declare. * config/arm/arm.c (clear_operation_p): New function. (cmse_clear_registers): Generate clear_multiple instruction pattern if targeting Armv8.1-M Mainline or successor. (output_return_instruction): Only output APSR register clearing if Armv8.1-M Mainline instructions not available. (thumb_exit): Likewise. * config/arm/predicates.md (clear_multiple_operation): New predicate. * config/arm/thumb2.md (clear_apsr): New define_insn. (clear_multiple): Likewise. * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec. *** gcc/testsuite/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu 2020-01-16 Thomas Preud'homme * gcc.target/arm/cmse/bitfield-1.c: Add check for CLRM. * gcc.target/arm/cmse/bitfield-2.c: Likewise. * gcc.target/arm/cmse/bitfield-3.c: Likewise. * gcc.target/arm/cmse/struct-1.c: Likewise. * gcc.target/arm/cmse/cmse-14.c: Likewise. * gcc.target/arm/cmse/cmse-1.c: Likewise. Restrict checks for Armv8-M GPR clearing when CLRM is not available. * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/union-1.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise. --- gcc/ChangeLog | 15 ++ gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 206 +++++++++++++++--- gcc/config/arm/predicates.md | 6 + gcc/config/arm/thumb2.md | 40 ++++ gcc/config/arm/unspecs.md | 1 + gcc/testsuite/ChangeLog | 38 ++++ .../gcc.target/arm/cmse/bitfield-1.c | 1 + .../gcc.target/arm/cmse/bitfield-2.c | 1 + .../gcc.target/arm/cmse/bitfield-3.c | 1 + gcc/testsuite/gcc.target/arm/cmse/cmse-1.c | 4 +- gcc/testsuite/gcc.target/arm/cmse/cmse-14.c | 1 + .../arm/cmse/mainline/8_1m/bitfield-4.c | 2 +- .../arm/cmse/mainline/8_1m/bitfield-5.c | 3 +- .../arm/cmse/mainline/8_1m/bitfield-6.c | 2 +- .../arm/cmse/mainline/8_1m/bitfield-7.c | 3 +- .../arm/cmse/mainline/8_1m/bitfield-8.c | 2 +- .../arm/cmse/mainline/8_1m/bitfield-9.c | 4 +- .../arm/cmse/mainline/8_1m/hard-sp/cmse-13.c | 5 +- .../arm/cmse/mainline/8_1m/hard-sp/cmse-5.c | 7 +- .../arm/cmse/mainline/8_1m/hard-sp/cmse-7.c | 5 +- .../arm/cmse/mainline/8_1m/hard-sp/cmse-8.c | 5 +- .../arm/cmse/mainline/8_1m/hard/cmse-13.c | 5 +- .../arm/cmse/mainline/8_1m/hard/cmse-5.c | 7 +- .../arm/cmse/mainline/8_1m/hard/cmse-7.c | 5 +- .../arm/cmse/mainline/8_1m/hard/cmse-8.c | 5 +- .../arm/cmse/mainline/8_1m/soft/cmse-13.c | 2 +- .../arm/cmse/mainline/8_1m/soft/cmse-5.c | 7 +- .../arm/cmse/mainline/8_1m/soft/cmse-7.c | 5 +- .../arm/cmse/mainline/8_1m/soft/cmse-8.c | 3 +- .../arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c | 6 +- .../arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c | 5 +- .../arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c | 3 +- .../arm/cmse/mainline/8_1m/softfp/cmse-13.c | 5 +- .../arm/cmse/mainline/8_1m/softfp/cmse-5.c | 7 +- .../arm/cmse/mainline/8_1m/softfp/cmse-7.c | 5 +- .../arm/cmse/mainline/8_1m/softfp/cmse-8.c | 3 +- .../arm/cmse/mainline/8_1m/union-1.c | 3 +- .../arm/cmse/mainline/8_1m/union-2.c | 2 +- .../arm/cmse/mainline/8m/softfp/cmse-13.c | 5 +- gcc/testsuite/gcc.target/arm/cmse/struct-1.c | 1 + 41 files changed, 311 insertions(+), 126 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 677a3ab9ef0..f3c94247f6a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,21 @@ 2020-01-16 Mihail-Calin Ionescu 2020-01-16 Thomas Preud'homme + * config/arm/arm-protos.h (clear_operation_p): Declare. + * config/arm/arm.c (clear_operation_p): New function. + (cmse_clear_registers): Generate clear_multiple instruction pattern if + targeting Armv8.1-M Mainline or successor. + (output_return_instruction): Only output APSR register clearing if + Armv8.1-M Mainline instructions not available. + (thumb_exit): Likewise. + * config/arm/predicates.md (clear_multiple_operation): New predicate. + * config/arm/thumb2.md (clear_apsr): New define_insn. + (clear_multiple): Likewise. + * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec. + +2020-01-16 Mihail-Calin Ionescu +2020-01-16 Thomas Preud'homme + * config/arm/arm.c (fp_sysreg_names): Declare and define. (use_return_insn): Also return false for Armv8.1-M Mainline. (output_return_instruction): Skip FPSCR clearing if Armv8.1-M diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 7c4b1003844..75793f61c04 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -83,6 +83,7 @@ extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT); extern int thumb1_legitimate_address_p (machine_mode, rtx, int); extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode, bool, bool); +extern bool clear_operation_p (rtx); extern int arm_const_double_rtx (rtx); extern int vfp3_const_double_rtx (rtx); extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 13633df7dd8..d035ad3ae80 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -13709,6 +13709,70 @@ ldm_stm_operation_p (rtx op, bool load, machine_mode mode, return true; } +/* Checks whether OP is a valid parallel pattern for a CLRM insn. To be a + valid CLRM pattern, OP must have the following form: + + [(set (reg:SI ) (const_int 0)) + (set (reg:SI ) (const_int 0)) + ... + (unspec_volatile [(const_int 0)] + VUNSPEC_CLRM_APSR) + (clobber (reg:CC CC_REGNUM)) + ] + + Any number (including 0) of set expressions is valid, the volatile unspec is + optional. All registers but SP and PC are allowed and registers must be in + strict increasing order. */ + +bool +clear_operation_p (rtx op) +{ + HOST_WIDE_INT i; + unsigned regno, last_regno; + rtx elt, reg, zero; + machine_mode mode; + HOST_WIDE_INT count = XVECLEN (op, 0); + + for (i = 0; i < count; i++) + { + elt = XVECEXP (op, 0, i); + + if (GET_CODE (elt) == UNSPEC_VOLATILE) + { + if (XINT (elt, 1) != VUNSPEC_CLRM_APSR + || XVECLEN (elt, 0) != 1 + || XVECEXP (elt, 0, 0) != CONST0_RTX (SImode) + || i != count - 2) + return false; + + continue; + } + + if (GET_CODE (elt) == CLOBBER) + continue; + + if (GET_CODE (elt) != SET) + return false; + + reg = SET_DEST (elt); + regno = REGNO (reg); + mode = GET_MODE (reg); + zero = SET_SRC (elt); + + if (!REG_P (reg) + || GET_MODE (reg) != SImode + || regno == SP_REGNUM + || regno == PC_REGNUM + || (i != 0 && regno <= last_regno) + || zero != CONST0_RTX (SImode)) + return false; + + last_regno = REGNO (reg); + } + + return true; +} + /* Return true iff it would be profitable to turn a sequence of NOPS loads or stores (depending on IS_STORE) into a load-multiple or store-multiple instruction. ADD_OFFSET is nonzero if the base address register needs @@ -18039,6 +18103,62 @@ cmse_clear_registers (sbitmap to_clear_bitmap, uint32_t *padding_bits_to_clear, /* Clear full registers. */ + if (TARGET_HAVE_FPCXT_CMSE) + { + rtvec vunspec_vec; + int i, j, k, nb_regs; + rtx use_seq, par, reg, set, vunspec; + int to_clear_bitmap_size = SBITMAP_SIZE (to_clear_bitmap); + auto_sbitmap core_regs_bitmap (to_clear_bitmap_size); + auto_sbitmap to_clear_core_bitmap (to_clear_bitmap_size); + + /* Get set of core registers to clear. */ + bitmap_clear (core_regs_bitmap); + bitmap_set_range (core_regs_bitmap, R0_REGNUM, + IP_REGNUM - R0_REGNUM + 1); + bitmap_and (to_clear_core_bitmap, to_clear_bitmap, + core_regs_bitmap); + gcc_assert (!bitmap_empty_p (to_clear_core_bitmap)); + + if (bitmap_empty_p (to_clear_core_bitmap)) + return; + + /* Create clrm RTX pattern. */ + nb_regs = bitmap_count_bits (to_clear_core_bitmap); + par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nb_regs + 2)); + + /* Insert core register clearing RTX in the pattern. */ + start_sequence (); + for (j = 0, i = minregno; j < nb_regs; i++) + { + if (!bitmap_bit_p (to_clear_core_bitmap, i)) + continue; + + reg = gen_rtx_REG (SImode, i); + set = gen_rtx_SET (reg, const0_rtx); + XVECEXP (par, 0, j++) = set; + emit_use (reg); + } + + /* Insert APSR register clearing RTX in the pattern + * along with clobbering CC. */ + vunspec_vec = gen_rtvec (1, gen_int_mode (0, SImode)); + vunspec = gen_rtx_UNSPEC_VOLATILE (SImode, vunspec_vec, + VUNSPEC_CLRM_APSR); + + XVECEXP (par, 0, j++) = vunspec; + + rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); + rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); + XVECEXP (par, 0, j) = clobber; + + use_seq = get_insns (); + end_sequence (); + + emit_insn_after (use_seq, emit_insn (par)); + minregno = FIRST_VFP_REGNUM; + } + /* If not marked for clearing, clearing_reg already does not contain any secret. */ if (clearing_regno <= maxregno @@ -20702,40 +20822,42 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, default: if (IS_CMSE_ENTRY (func_type)) { - /* Check if we have to clear the 'GE bits' which is only used if - parallel add and subtraction instructions are available. */ - if (TARGET_INT_SIMD) - snprintf (instr, sizeof (instr), - "msr%s\tAPSR_nzcvqg, %%|lr", conditional); - else - snprintf (instr, sizeof (instr), - "msr%s\tAPSR_nzcvq, %%|lr", conditional); - - output_asm_insn (instr, & operand); - /* Do not clear FPSCR if targeting Armv8.1-M Mainline, VLDR takes - care of it. */ - if (TARGET_HARD_FLOAT && ! TARGET_HAVE_FPCXT_CMSE) + /* For Armv8.1-M, this is cleared as part of the CLRM instruction + emitted by cmse_nonsecure_entry_clear_before_return () and the + VSTR/VLDR instructions in the prologue and epilogue. */ + if (!TARGET_HAVE_FPCXT_CMSE) { - /* Clear the cumulative exception-status bits (0-4,7) and the - condition code bits (28-31) of the FPSCR. We need to - remember to clear the first scratch register used (IP) and - save and restore the second (r4). */ - snprintf (instr, sizeof (instr), "push\t{%%|r4}"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "vmrs\t%%|ip, fpscr"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "movw\t%%|r4, #65376"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "movt\t%%|r4, #4095"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "and\t%%|ip, %%|r4"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "vmsr\tfpscr, %%|ip"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "pop\t{%%|r4}"); - output_asm_insn (instr, & operand); - snprintf (instr, sizeof (instr), "mov\t%%|ip, %%|lr"); + /* Check if we have to clear the 'GE bits' which is only used if + parallel add and subtraction instructions are available. */ + if (TARGET_INT_SIMD) + snprintf (instr, sizeof (instr), + "msr%s\tAPSR_nzcvqg, %%|lr", conditional); + else + snprintf (instr, sizeof (instr), + "msr%s\tAPSR_nzcvq, %%|lr", conditional); + output_asm_insn (instr, & operand); + /* Do not clear FPSCR if targeting Armv8.1-M Mainline, VLDR takes + care of it. */ + if (TARGET_HARD_FLOAT) + { + /* Clear the cumulative exception-status bits (0-4,7) and + the condition code bits (28-31) of the FPSCR. We need + to remember to clear the first scratch register used + (IP) and save and restore the second (r4). + + Important note: the length of the + thumb2_cmse_entry_return insn pattern must account for + the size of the below instructions. */ + output_asm_insn ("push\t{%|r4}", & operand); + output_asm_insn ("vmrs\t%|ip, fpscr", & operand); + output_asm_insn ("movw\t%|r4, #65376", & operand); + output_asm_insn ("movt\t%|r4, #4095", & operand); + output_asm_insn ("and\t%|ip, %|r4", & operand); + output_asm_insn ("vmsr\tfpscr, %|ip", & operand); + output_asm_insn ("pop\t{%|r4}", & operand); + output_asm_insn ("mov\t%|ip, %|lr", & operand); + } } snprintf (instr, sizeof (instr), "bxns\t%%|lr"); } @@ -22718,6 +22840,9 @@ arm_expand_prologue (void) saved_regs += 4; insn = emit_insn (gen_push_fpsysreg_insn (stack_pointer_rtx, GEN_INT (FPCXTNS_ENUM))); + rtx dwarf = gen_rtx_SET (stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, -4)); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); RTX_FRAME_RELATED_P (insn) = 1; } @@ -25134,8 +25259,11 @@ thumb_exit (FILE *f, int reg_containing_return_addr) if (IS_CMSE_ENTRY (arm_current_func_type ())) { - asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n", - reg_containing_return_addr); + /* For Armv8.1-M, this is cleared as part of the CLRM instruction + emitted by cmse_nonsecure_entry_clear_before_return (). */ + if (!TARGET_HAVE_FPCXT_CMSE) + asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n", + reg_containing_return_addr); asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr); } else @@ -25375,11 +25503,14 @@ thumb_exit (FILE *f, int reg_containing_return_addr) address. It may therefore contain information that we might not want to leak, hence it must be cleared. The value in R0 will never be a secret at this point, so it is safe to use it, see the clearing code - in 'cmse_nonsecure_entry_clear_before_return'. */ + in cmse_nonsecure_entry_clear_before_return (). */ if (reg_containing_return_addr != LR_REGNUM) asm_fprintf (f, "\tmov\tlr, r0\n"); - asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n", reg_containing_return_addr); + /* For Armv8.1-M, this is cleared as part of the CLRM instruction emitted + by cmse_nonsecure_entry_clear_before_return (). */ + if (!TARGET_HAVE_FPCXT_CMSE) + asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n", reg_containing_return_addr); asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr); } else @@ -26917,6 +27048,9 @@ arm_expand_epilogue (bool really_return) insn = emit_insn (gen_pop_fpsysreg_insn (stack_pointer_rtx, GEN_INT (FPCXTNS_ENUM))); + rtx dwarf = gen_rtx_SET (stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, 4)); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); RTX_FRAME_RELATED_P (insn) = 1; } } diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index d5da5027519..6f4f1a18986 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -545,6 +545,12 @@ (match_test "satisfies_constraint_Dy (op)") (match_test "satisfies_constraint_G (op)")))) +(define_special_predicate "clear_multiple_operation" + (match_code "parallel") +{ + return clear_operation_p (op); +}) + (define_special_predicate "load_multiple_operation" (match_code "parallel") { diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 5ce03997c38..6866b4e7f80 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1576,3 +1576,43 @@ FAIL; }") +(define_insn "*clear_apsr" + [(unspec_volatile:SI [(const_int 0)] VUNSPEC_CLRM_APSR) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2 && TARGET_HAVE_FPCXT_CMSE && use_cmse" + "clrm%?\\t{APSR}" + [(set_attr "predicable" "yes")] +) + +;; The operands are validated through the clear_multiple_operation +;; match_parallel predicate rather than through constraints so enable it only +;; after reload. +(define_insn "*clear_multiple" + [(match_parallel 0 "clear_multiple_operation" + [(set (match_operand:SI 1 "register_operand" "") + (const_int 0))])] + "TARGET_THUMB2 && TARGET_HAVE_FPCXT_CMSE && use_cmse && reload_completed" + { + char pattern[100]; + int i, num_saves = XVECLEN (operands[0], 0); + + strcpy (pattern, \"clrm%?\\t{\"); + for (i = 0; i < num_saves; i++) + { + if (GET_CODE (XVECEXP (operands[0], 0, i)) == UNSPEC_VOLATILE) + { + strcat (pattern, \"APSR\"); + ++i; + } + else + strcat (pattern, + reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, i), 0))]); + if (i < num_saves - 1) + strcat (pattern, \", %|\"); + } + strcat (pattern, \"}\"); + output_asm_insn (pattern, operands); + return \"\"; + } + [(set_attr "predicable" "yes")] +) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 40f6a8b7161..e039c506369 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -240,6 +240,7 @@ VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier. VUNSPEC_APSR_WRITE ; Represent writing the APSR. VUNSPEC_VSTR_VLDR ; Represent the vstr/vldr instruction. + VUNSPEC_CLRM_APSR ; Represent the clearing of APSR with clrm instruction. ]) ;; Enumerators for NEON unspecs. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 200b1cfffbe..195fc02e73c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,6 +1,44 @@ 2020-01-16 Mihail-Calin Ionescu 2020-01-16 Thomas Preud'homme + * gcc.target/arm/cmse/bitfield-1.c: Add check for CLRM. + * gcc.target/arm/cmse/bitfield-2.c: Likewise. + * gcc.target/arm/cmse/bitfield-3.c: Likewise. + * gcc.target/arm/cmse/struct-1.c: Likewise. + * gcc.target/arm/cmse/cmse-14.c: Likewise. + * gcc.target/arm/cmse/cmse-1.c: Likewise. Restrict checks for Armv8-M + GPR clearing when CLRM is not available. + * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: likewise. + * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: likewise. + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/union-1.c: Likewise. + * gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise. + +2020-01-16 Mihail-Calin Ionescu +2020-01-16 Thomas Preud'homme + * gcc.target/arm/cmse/bitfield-1.c: add checks for VSTR and VLDR. * gcc.target/arm/cmse/bitfield-2.c: Likewise. * gcc.target/arm/cmse/bitfield-3.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c b/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c index 6d611e130b6..7036cb9508c 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c +++ b/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c @@ -36,6 +36,7 @@ main (void) /* { dg-final { scan-assembler "movw\tr1, #1855" } } */ /* { dg-final { scan-assembler "movt\tr1, 65535" } } */ /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c b/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c index b7ec0a04031..50d4979470d 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c +++ b/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c @@ -33,6 +33,7 @@ main (void) /* { dg-final { scan-assembler "movw\tr1, #1919" } } */ /* { dg-final { scan-assembler "movt\tr1, 2047" } } */ /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c b/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c index 7b9c3f0fe06..2b7507c900a 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c +++ b/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c @@ -34,5 +34,6 @@ main (void) /* { dg-final { scan-assembler "movw\tr1, #65535" } } */ /* { dg-final { scan-assembler "movt\tr1, 63" } } */ /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c index aa0ec8e0b0f..35cab1f3233 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c @@ -105,8 +105,10 @@ qux (int_nsfunc_t * callback) /* { dg-final { scan-assembler "bic" } } */ /* { dg-final { scan-assembler "push\t\{r4, r5, r6" } } */ /* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvq" } } */ +/* { dg-final { scan-assembler "msr\tAPSR_nzcvq" { target { ! arm_cmse_clear_ok } } } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" { target arm_cmse_clear_ok } } } */ int call_callback (void) { diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-14.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-14.c index df1ea52bec5..1f5af7c2dba 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/cmse-14.c +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-14.c @@ -9,5 +9,6 @@ int foo (void) return bar (); } +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ /* { dg-final { scan-assembler-not "^(.*\\s)?bl?\[^\\s]*\\s+bar" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c index 62c63b888ab..c52e1c14d99 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c @@ -12,5 +12,5 @@ /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c index b718a70522b..fdba955a32f 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c @@ -10,6 +10,5 @@ /* { dg-final { scan-assembler "and\tr1, r1, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c index 16536ab4f9e..85068ceaac6 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c @@ -13,5 +13,5 @@ /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c index 0b3cc1e2b2b..af69d38acf4 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c @@ -10,6 +10,5 @@ /* { dg-final { scan-assembler "and\tr1, r1, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c index 914ea39626f..62201595549 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c @@ -13,5 +13,5 @@ /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c index 32435d25580..287f0d6faad 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c @@ -7,7 +7,5 @@ /* { dg-final { scan-assembler "and\tr0, r0, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c index eb655b5504e..7b2df1faff5 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts2, #1\.0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c index ab266af7092..638643d0a67 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c @@ -6,10 +6,6 @@ #include "../../../cmse-5.x" /* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */ -/* { dg-final { scan-assembler "mov\tr0, lr" } } */ -/* { dg-final { scan-assembler "mov\tr1, lr" } } */ -/* { dg-final { scan-assembler "mov\tr2, lr" } } */ -/* { dg-final { scan-assembler "mov\tr3, lr" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */ @@ -26,7 +22,6 @@ /* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, ip, APSR\}" } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c index fd1a24b3258..9ec14d1a707 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c index d8f9b7758d5..d375879ed02 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c index 4878c6ef915..e5cb0fabd4c 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c index 82aad2d13d6..7e3b7609dfa 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c @@ -6,10 +6,6 @@ #include "../../../cmse-5.x" /* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */ -/* { dg-final { scan-assembler "mov\tr0, lr" } } */ -/* { dg-final { scan-assembler "mov\tr1, lr" } } */ -/* { dg-final { scan-assembler "mov\tr2, lr" } } */ -/* { dg-final { scan-assembler "mov\tr3, lr" } } */ /* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */ @@ -19,7 +15,6 @@ /* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, ip, APSR\}" } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c index 8e054c2aeeb..d998b43a148 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c index e74cea7697b..e416bef2cb9 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c index 4c4a0c956fa..d43a9f85a19 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c @@ -8,9 +8,9 @@ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ /* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ /* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ /* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, APSR\}" } } */ /* { dg-final { scan-assembler-not "vmov" } } */ /* { dg-final { scan-assembler-not "vmsr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c index c684d79fae0..157bccb9ff3 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c @@ -5,13 +5,8 @@ #include "../../../cmse-5.x" /* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */ -/* { dg-final { scan-assembler "mov\tr1, lr" } } */ -/* { dg-final { scan-assembler "mov\tr2, lr" } } */ -/* { dg-final { scan-assembler "mov\tr3, lr" } } */ -/* { dg-final { scan-assembler "mov\tip, lr" } } */ /* { dg-final { scan-assembler-not "vmov" } } */ /* { dg-final { scan-assembler-not "vmsr" } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c index 4cb6a54a0a5..02e48157a2c 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c @@ -7,10 +7,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler-not "vmov" } } */ /* { dg-final { scan-assembler-not "vmsr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c index 4764b2fadfb..c7a22a2ba46 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c @@ -9,8 +9,7 @@ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ /* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ /* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler-not "vmov" } } */ /* { dg-final { scan-assembler-not "vmsr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c index 9b2e7565d24..2522a17a631 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c @@ -8,9 +8,6 @@ /* { dg-final { scan-assembler "__acle_se_foo:" } } */ /* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */ /* { dg-final { scan-assembler-not "mov\tr0, lr" } } */ -/* { dg-final { scan-assembler "mov\tr1, lr" } } */ -/* { dg-final { scan-assembler "mov\tr2, lr" } } */ -/* { dg-final { scan-assembler "mov\tr3, lr" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */ @@ -27,7 +24,6 @@ /* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c index 9e93d75c35d..d34ca383236 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* Now we check that we use the correct intrinsic to call. */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c index 566889e66c8..ff8e9816cff 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c @@ -10,8 +10,7 @@ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ /* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ /* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r2, r3, APSR\}" } } */ /* Now we check that we use the correct intrinsic to call. */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c index 0ee28de4123..ff9a7dfa5e6 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c @@ -9,8 +9,9 @@ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ /* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "\n\tmov\tr1, r4" } } */ -/* { dg-final { scan-assembler-not "\n\tmov\tr2, r4\n\tmov\tr3, r4" } } */ +/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ +/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, APSR\}" } } */ /* Now we check that we use the correct intrinsic to call. */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c index 5af1fdb934c..eb7561f2a26 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c @@ -7,10 +7,6 @@ /* { dg-final { scan-assembler "__acle_se_foo:" } } */ /* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */ -/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */ -/* { dg-final { scan-assembler "mov\tr1, lr" } } */ -/* { dg-final { scan-assembler "mov\tr2, lr" } } */ -/* { dg-final { scan-assembler "mov\tr3, lr" } } */ /* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */ @@ -19,7 +15,6 @@ /* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */ /* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */ -/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */ /* { dg-final { scan-assembler "bxns" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c index 1c38290e79d..03d36aa6509 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c @@ -8,10 +8,7 @@ /* Checks for saving and clearing prior to function call. */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */ /* Now we check that we use the correct intrinsic to call. */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c index 39c2e72f968..ce45e10688f 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c @@ -10,8 +10,7 @@ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ /* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ /* { dg-final { scan-assembler-not "mov\tr1, r4" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r2, r3, APSR\}" } } */ /* Now we check that we use the correct intrinsic to call. */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-1.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-1.c index d51db020c77..dbd1d34413e 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-1.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-1.c @@ -10,6 +10,5 @@ /* { dg-final { scan-assembler "and\tr1, r1, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr2, r4" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r2, r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c index 131afbbf428..3edc7f1e259 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c @@ -14,5 +14,5 @@ /* { dg-final { scan-assembler "and\tr2, r2, ip" } } */ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ -/* { dg-final { scan-assembler "mov\tr3, r4" } } */ +/* { dg-final { scan-assembler "clrm\t\{r3, APSR\}" } } */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c index 0ee28de4123..3a72406df24 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c +++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c @@ -9,8 +9,9 @@ /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */ /* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */ /* { dg-final { scan-assembler-not "mov\tr0, r4" } } */ -/* { dg-final { scan-assembler "\n\tmov\tr1, r4" } } */ -/* { dg-final { scan-assembler-not "\n\tmov\tr2, r4\n\tmov\tr3, r4" } } */ +/* { dg-final { scan-assembler "mov\tr1, r4" } } */ +/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */ +/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */ /* Now we check that we use the correct intrinsic to call. */ /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/struct-1.c b/gcc/testsuite/gcc.target/arm/cmse/struct-1.c index 5f6891a26d9..90fdac18e30 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/struct-1.c +++ b/gcc/testsuite/gcc.target/arm/cmse/struct-1.c @@ -29,5 +29,6 @@ main (void) /* { dg-final { scan-assembler "movs\tr1, #255" } } */ /* { dg-final { scan-assembler "movt\tr1, 65535" } } */ /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */ +/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */ /* { dg-final { scan-assembler "bxns" } } */ -- 2.30.2