From 9735bd5bf2c78ec3d3cf40bcd240783755a9be05 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 1 Mar 2020 20:50:13 +0100 Subject: [PATCH] integration/soc: add add_ethernet method. --- litex/soc/integration/soc.py | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index a0ee9e14..021b7a19 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1009,3 +1009,27 @@ class LiteXSoC(SoC): # Wishbone Slave <--> LiteDRAM bridge self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port, base_address = self.bus.regions["main_ram"].origin) + + # Add Ethernet --------------------------------------------------------------------------------- + def add_ethernet(self, phy): + # Imports + from liteeth.mac import LiteEthMAC + # PHY + self.add_csr("ethphy") + # MAC + self.submodules.ethmac = LiteEthMAC( + phy = phy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) + ethmac_region = SoCRegion(size=0x2000, cached=False) + self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) + self.add_csr("ethmac") + self.add_interrupt("ethmac") + # Timing constraints + self.platform.add_period_constraint(phy.crg.cd_eth_rx.clk, 1e9/phy.rx_clk_freq) + self.platform.add_period_constraint(phy.crg.cd_eth_tx.clk, 1e9/phy.tx_clk_freq) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + phy.crg.cd_eth_rx.clk, + phy.crg.cd_eth_tx.clk) -- 2.30.2