From 9749c70730f7859eb26af61e9abdb1cb5c78be97 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 7 Nov 2019 08:20:27 +0000 Subject: [PATCH] hdl.ir: lower domains before resolving hierarchy conflicts. Otherwise, two subfragments with the same local clock domain would not be able to drive its clock or reset signals. This can be easily hit if using two ResetSynchronizers in one module. Fixes #265. --- nmigen/hdl/ir.py | 2 +- nmigen/test/test_hdl_ir.py | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py index c213943..1df1b87 100644 --- a/nmigen/hdl/ir.py +++ b/nmigen/hdl/ir.py @@ -540,8 +540,8 @@ class Fragment: fragment = SampleLowerer()(self) new_domains = fragment._propagate_domains(missing_domain) - fragment._resolve_hierarchy_conflicts() fragment = DomainLowerer()(fragment) + fragment._resolve_hierarchy_conflicts() if ports is None: fragment._propagate_ports(ports=(), all_undef_as_ports=True) else: diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py index 5c86b64..74a9096 100644 --- a/nmigen/test/test_hdl_ir.py +++ b/nmigen/test/test_hdl_ir.py @@ -642,6 +642,20 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase): self.f1._resolve_hierarchy_conflicts(mode="silent") self.assertEqual(self.f1.subfragments, []) + def test_no_conflict_local_domains(self): + f1 = Fragment() + cd1 = ClockDomain("d", local=True) + f1.add_domains(cd1) + f1.add_driver(ClockSignal("d")) + f2 = Fragment() + cd2 = ClockDomain("d", local=True) + f2.add_domains(cd2) + f2.add_driver(ClockSignal("d")) + f3 = Fragment() + f3.add_subfragment(f1) + f3.add_subfragment(f2) + f3.prepare() + class InstanceTestCase(FHDLTestCase): def test_construct(self): -- 2.30.2