From 975bd9be8bc0f44fc24b8249ed20010610ee7f46 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 7 Oct 2019 08:49:32 +0200 Subject: [PATCH] cpu/vexriscv: use specific mem_map for linux variant --- litex/soc/cores/cpu/vexriscv/core.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index e70f3865..3ae10fb8 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -81,6 +81,15 @@ class VexRiscv(CPU, AutoCSR): gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") linker_output_format = "elf32-littleriscv" + @property + def mem_map_linux(self): + return { + "rom": 0x00000000, + "sram": 0x10000000, + "main_ram": 0xc0000000, + "csr": 0xf0000000, + } + @property def gcc_flags(self): flags = GCC_FLAGS[self.variant] @@ -132,6 +141,7 @@ class VexRiscv(CPU, AutoCSR): if "linux" in variant: self.add_timer() + self.mem_map = self.mem_map_linux if "debug" in variant: self.add_debug() -- 2.30.2