From 975be6686fc06ca3364d8ce32edd14eada56aa14 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Oct 2018 15:37:34 +0200 Subject: [PATCH] platforms/genesys2: add eth clock timing constraint --- litex/boards/platforms/genesys2.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index 0a454ab8..89f72120 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -117,3 +117,7 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) + try: + self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) + except ConstraintError: + pass -- 2.30.2