From 97755701afbdc34215954008d6550065631ca826 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 15 Sep 2015 13:09:45 +0000 Subject: [PATCH] [AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregs * config/aarch64/aarch64-simd.md (aarch64_ld2r, aarch64_ld3r, aarch64_ld4r): Combine together, making... (aarch64_simd_ldr): ...this. (aarch64_ld2_lane, aarch64_ld3_lane, aarch64_ld4_lane): Combine together, making... (aarch64_ld_lane): ...this. (aarch64_st2_lane, aarch64_st3_lane, aarch64_st4_lane): Combine together, making... (aarch64_st_lane): ...this. * config/aarch64/iterators.md (nregs): Add comment. From-SVN: r227793 --- gcc/ChangeLog | 13 +++ gcc/config/aarch64/aarch64-simd.md | 138 +++++------------------------ gcc/config/aarch64/iterators.md | 3 + 3 files changed, 39 insertions(+), 115 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c1c2c5f1651..a4911a0ff6a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2015-09-15 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_ld2r, + aarch64_ld3r, aarch64_ld4r): Combine together, making... + (aarch64_simd_ldr): ...this. + (aarch64_ld2_lane, aarch64_ld3_lane, + aarch64_ld4_lane): Combine together, making... + (aarch64_ld_lane): ...this. + (aarch64_st2_lane, aarch64_st3_lane, + aarch64_st4_lane): Combine together, making... + (aarch64_st_lane): ...this. + * config/aarch64/iterators.md (nregs): Add comment. + 2015-09-15 Alan Lawrence * config/aarch64/aarch64-simd.md (aarch64_simd_ld2r): diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f239ee74226..dbe52591b59 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4381,42 +4381,18 @@ FAIL; }) -(define_expand "aarch64_ld2r" - [(match_operand:OI 0 "register_operand" "=w") +(define_expand "aarch64_ldr" + [(match_operand:VSTRUCT 0 "register_operand" "=w") (match_operand:DI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) + * ); - emit_insn (gen_aarch64_simd_ld2r (operands[0], mem)); - DONE; -}) - -(define_expand "aarch64_ld3r" - [(match_operand:CI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); - - emit_insn (gen_aarch64_simd_ld3r (operands[0], mem)); - DONE; -}) - -(define_expand "aarch64_ld4r" - [(match_operand:XI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); - - emit_insn (gen_aarch64_simd_ld4r (operands[0],mem)); + emit_insn (gen_aarch64_simd_ldr (operands[0], + mem)); DONE; }) @@ -4599,62 +4575,26 @@ DONE; }) -(define_expand "aarch64_ld2_lane" - [(match_operand:OI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (match_operand:OI 2 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); - - emit_insn (gen_aarch64_vec_load_lanesoi_lane (operands[0], - mem, - operands[2], - operands[3])); - DONE; -}) - -(define_expand "aarch64_ld3_lane" - [(match_operand:CI 0 "register_operand" "=w") +(define_expand "aarch64_ld_lane" + [(match_operand:VSTRUCT 0 "register_operand" "=w") (match_operand:DI 1 "register_operand" "w") - (match_operand:CI 2 "register_operand" "0") + (match_operand:VSTRUCT 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); - - emit_insn (gen_aarch64_vec_load_lanesci_lane (operands[0], - mem, - operands[2], - operands[3])); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) + * ); + + aarch64_simd_lane_bounds (operands[3], 0, + GET_MODE_NUNITS (mode), + NULL); + emit_insn (gen_aarch64_vec_load_lanes_lane ( + operands[0], mem, operands[2], operands[3])); DONE; }) -(define_expand "aarch64_ld4_lane" - [(match_operand:XI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (match_operand:XI 2 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); - - emit_insn (gen_aarch64_vec_load_lanesxi_lane (operands[0], - mem, - operands[2], - operands[3])); - DONE; -}) - - - ;; Expanders for builtins to extract vector registers from large ;; opaque integer modes. @@ -4882,51 +4822,19 @@ DONE; }) -(define_expand "aarch64_st2_lane" - [(match_operand:DI 0 "register_operand" "r") - (match_operand:OI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand")] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[0]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); - - emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, - operands[1], - operands[2])); - DONE; -}) - -(define_expand "aarch64_st3_lane" - [(match_operand:DI 0 "register_operand" "r") - (match_operand:CI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand")] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[0]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); - - emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, - operands[1], - operands[2])); - DONE; -}) - -(define_expand "aarch64_st4_lane" +(define_expand "aarch64_st_lane" [(match_operand:DI 0 "register_operand" "r") - (match_operand:XI 1 "register_operand" "w") + (match_operand:VSTRUCT 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { rtx mem = gen_rtx_MEM (BLKmode, operands[0]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) + * ); - emit_insn (gen_aarch64_vec_store_lanesxi_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanes_lane ( + mem, operands[1], operands[2])); DONE; }) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index aab164ad062..38c5a2424e4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -577,6 +577,9 @@ (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) +;; This is both the number of Q-Registers needed to hold the corresponding +;; opaque large integer mode, and the number of elements touched by the +;; ld..._lane and st..._lane operations. (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI") -- 2.30.2