From 9790cfcefa6cbf1aeb898757e5c9be6d5eecc425 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Tue, 12 Dec 2017 20:24:57 -0800 Subject: [PATCH] anv,iris: L3ALLOC register replaces L3CNTLREG for gen12 Signed-off-by: Jordan Justen Reviewed-by: Kenneth Graunke --- src/gallium/drivers/iris/iris_state.c | 15 +++++++++++++-- src/intel/genxml/gen12.xml | 7 +++---- src/intel/vulkan/genX_cmd_buffer.c | 16 +++++++++++++--- 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index ec1e56fe356..c63732c4acc 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -607,8 +607,19 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg, bool has_slm, bool wants_dc_cache) { uint32_t reg_val; - iris_pack_state(GENX(L3CNTLREG), ®_val, reg) { + +#if GEN_GEN >= 12 +#define L3_ALLOCATION_REG GENX(L3ALLOC) +#define L3_ALLOCATION_REG_num GENX(L3ALLOC_num) +#else +#define L3_ALLOCATION_REG GENX(L3CNTLREG) +#define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num) +#endif + + iris_pack_state(L3_ALLOCATION_REG, ®_val, reg) { +#if GEN_GEN < 12 reg.SLMEnable = has_slm; +#endif #if GEN_GEN == 11 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set * in L3CNTLREG register. The default setting of the bit is not the @@ -622,7 +633,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg, reg.DCAllocation = cfg->n[GEN_L3P_DC]; reg.AllAllocation = cfg->n[GEN_L3P_ALL]; } - iris_emit_lri(batch, L3CNTLREG, reg_val); + _iris_emit_lri(batch, L3_ALLOCATION_REG_num, reg_val); } static void diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 98a7bca74cd..599b3486200 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6991,11 +6991,10 @@ - - + + - - + diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 10da132115c..dd0f6e20681 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1627,7 +1627,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, gen_dump_l3_config(cfg, stderr); } - const bool has_slm = cfg->n[GEN_L3P_SLM]; + UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM]; /* According to the hardware docs, the L3 partitioning can only be changed * while the pipeline is completely drained and the caches are flushed, @@ -1674,9 +1674,19 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]); +#if GEN_GEN >= 12 +#define L3_ALLOCATION_REG GENX(L3ALLOC) +#define L3_ALLOCATION_REG_num GENX(L3ALLOC_num) +#else +#define L3_ALLOCATION_REG GENX(L3CNTLREG) +#define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num) +#endif + uint32_t l3cr; - anv_pack_struct(&l3cr, GENX(L3CNTLREG), + anv_pack_struct(&l3cr, L3_ALLOCATION_REG, +#if GEN_GEN < 12 .SLMEnable = has_slm, +#endif #if GEN_GEN == 11 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set * in L3CNTLREG register. The default setting of the bit is not the @@ -1691,7 +1701,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, .AllAllocation = cfg->n[GEN_L3P_ALL]); /* Set up the L3 partitioning. */ - emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG_num), l3cr); + emit_lri(&cmd_buffer->batch, L3_ALLOCATION_REG_num, l3cr); #else -- 2.30.2