From 97958abd1eae81b1cc74abd85d16c5d29fd75791 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 18 Aug 2022 01:00:12 +0100 Subject: [PATCH] use bitpattern in minor_30.csv to give a single match for rldic and others. two lines were being used 0000 and 0001, replaced with 000- --- openpower/isatables/insndb.csv | 2 +- openpower/isatables/minor_30.csv | 16 ++++++---------- src/openpower/decoder/power_decoder.py | 2 +- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/openpower/isatables/insndb.csv b/openpower/isatables/insndb.csv index 86521015..a48de1f8 100644 --- a/openpower/isatables/insndb.csv +++ b/openpower/isatables/insndb.csv @@ -1,6 +1,6 @@ path,opcode,bitsel,suffix,mode minor_19.csv,19,21:30,NONE,integer -minor_30.csv,30,27:30,NONE,integer +minor_30.csv,30,27:30,NONE,pattern minor_31.csv,31,21:30,0b101,integer minor_58.csv,58,30:31,NONE,integer minor_62.csv,62,30:31,NONE,integer diff --git a/openpower/isatables/minor_30.csv b/openpower/isatables/minor_30.csv index a954ddf0..cb68d552 100644 --- a/openpower/isatables/minor_30.csv +++ b/openpower/isatables/minor_30.csv @@ -1,13 +1,9 @@ # SPDX-License-Header: CC-BY-4 # derived from microwatt decode1.vhdl, with thanks and gratitude (IBM, OPF) opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS -0b0100,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD, -0b0101,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD, -0b0000,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS, -0b0001,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS, -0b0010,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD, -0b0011,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD, -0b0110,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD, -0b0111,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD, -0b1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD, -0b1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD, +010-,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD, +000-,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS, +001-,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD, +011-,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD, +1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD, +1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD, diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py index 7e629632..9da38df7 100644 --- a/src/openpower/decoder/power_decoder.py +++ b/src/openpower/decoder/power_decoder.py @@ -729,7 +729,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None, pminor = [ m19, Subdecoder(pattern=30, opcodes=get_csv("minor_30.csv"), - opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]), + opint=False, bitsel=(1, 5), suffix=None, subdecoders=[]), Subdecoder(pattern=31, opcodes=get_csv("minor_31.csv"), opint=True, bitsel=(1, 11), suffix=0b00101, subdecoders=[]), Subdecoder(pattern=58, opcodes=get_csv("minor_58.csv"), -- 2.30.2