From 97cfe6e6900867d08d1a44956cc752b8ec19c46d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Jun 2019 07:29:51 +0100
Subject: [PATCH] add comment on sv.setvl

---
 simple_v_extension/specification/sv.setvl.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 7c200b215..eced4438f 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -108,3 +108,7 @@ It leaves space for future expansion to RV128 and/or multi-register predicates.
         // rd is not x0
         regs[rd] = vl
     }
+
+# links
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001881.html>
-- 
2.30.2