From 97d03c2b3b3c5bee9685786f17d1d14ab77c6f6e Mon Sep 17 00:00:00 2001 From: Patrick Urban Date: Mon, 18 Oct 2021 10:46:18 +0200 Subject: [PATCH] synth_gatemate: Apply new test practice with assert-max --- tests/arch/gatemate/add_sub.ys | 2 +- tests/arch/gatemate/adffs.ys | 4 ++-- tests/arch/gatemate/fsm.ys | 6 +++--- tests/arch/gatemate/latches.ys | 2 +- tests/arch/gatemate/logic.ys | 6 +++--- tests/arch/gatemate/mul.ys | 2 +- tests/arch/gatemate/tribuf.ys | 2 +- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys index c0055e521..bf261ba5a 100644 --- a/tests/arch/gatemate/add_sub.ys +++ b/tests/arch/gatemate/add_sub.ys @@ -5,5 +5,5 @@ equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivale design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:CC_ADDF -select -assert-count 4 t:CC_LUT1 +select -assert-max 4 t:CC_LUT1 select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys index 3f9401d68..b2ded6e9d 100644 --- a/tests/arch/gatemate/adffs.ys +++ b/tests/arch/gatemate/adffs.ys @@ -28,7 +28,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:CC_BUFG select -assert-count 1 t:CC_DFF -select -assert-count 1 t:CC_LUT2 +select -assert-max 1 t:CC_LUT2 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D design -load read @@ -39,5 +39,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:CC_BUFG select -assert-count 1 t:CC_DFF -select -assert-count 1 t:CC_LUT2 +select -assert-max 1 t:CC_LUT2 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys index 6e3e3a1be..6b43ead7a 100644 --- a/tests/arch/gatemate/fsm.ys +++ b/tests/arch/gatemate/fsm.ys @@ -14,7 +14,7 @@ cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:CC_BUFG select -assert-count 6 t:CC_DFF -select -assert-count 4 t:CC_LUT2 -select -assert-count 2 t:CC_LUT3 -select -assert-count 8 t:CC_LUT4 +select -assert-max 5 t:CC_LUT2 +select -assert-max 4 t:CC_LUT3 +select -assert-max 9 t:CC_LUT4 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys index 807650b81..5f64c6db5 100644 --- a/tests/arch/gatemate/latches.ys +++ b/tests/arch/gatemate/latches.ys @@ -25,5 +25,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:CC_DLT -select -assert-count 2 t:CC_LUT3 +select -assert-max 2 t:CC_LUT3 select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys index 2718375a2..026406bc8 100644 --- a/tests/arch/gatemate/logic.ys +++ b/tests/arch/gatemate/logic.ys @@ -4,7 +4,7 @@ proc equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:CC_LUT1 -select -assert-count 6 t:CC_LUT2 -select -assert-count 2 t:CC_LUT4 +select -assert-max 1 t:CC_LUT1 +select -assert-max 6 t:CC_LUT2 +select -assert-max 2 t:CC_LUT4 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys index d10d07f1e..ded5fe729 100644 --- a/tests/arch/gatemate/mul.ys +++ b/tests/arch/gatemate/mul.ys @@ -28,6 +28,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mul_unsigned_sync # Constrain all select calls below inside the top module select -assert-count 1 t:CC_MULT select -assert-count 1 t:CC_BUFG -select -assert-count 18 t:CC_LUT4 +select -assert-max 18 t:CC_LUT4 select -assert-count 18 t:CC_DFF select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/tribuf.ys b/tests/arch/gatemate/tribuf.ys index 96cb05bfe..d900fa5e4 100644 --- a/tests/arch/gatemate/tribuf.ys +++ b/tests/arch/gatemate/tribuf.ys @@ -8,6 +8,6 @@ equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate # design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 2 t:CC_IBUF -select -assert-count 1 t:CC_LUT1 +select -assert-max 1 t:CC_LUT1 select -assert-count 1 t:CC_TOBUF select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D -- 2.30.2