From 97ddcfff7c50347b13701a156f9ac4942e0caaf7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Thu, 28 Jun 2018 21:03:39 +0200 Subject: [PATCH] amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not support Acked-by: Bas Nieuwenhuizen --- src/amd/addrlib/src/gfx10/gfx10addrlib.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp index 63aabcab096..cecd1535568 100644 --- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp +++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp @@ -388,10 +388,9 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeDccInfo( { ADDR_E_RETURNCODE ret = ADDR_OK; - if (IsLinear(pIn->swizzleMode) || IsBlock256b(pIn->swizzleMode)) + if (pIn->swizzleMode != ADDR_SW_64KB_Z_X && pIn->swizzleMode != ADDR_SW_64KB_R_X) { - // Hardware support dcc for 256 swizzle mode, but address lib will not support it because we only - // select 256 swizzle mode for small surface, and it's not helpful to enable dcc for small surface. + // Hardware does not support DCC for this swizzle mode. ret = ADDR_INVALIDPARAMS; } else if (m_settings.dccUnsup3DSwDis && IsTex3d(pIn->resourceType) && IsDisplaySwizzle(pIn->swizzleMode)) -- 2.30.2