From 97e534d0b6d42d79b9a3d088490f1c159b1107df Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 2 May 2020 12:04:46 +0200 Subject: [PATCH] cpus: add nop instruction and use it to simplify the BIOS. --- litex/soc/cores/cpu/blackparrot/core.py | 1 + litex/soc/cores/cpu/lm32/core.py | 1 + litex/soc/cores/cpu/microwatt/core.py | 1 + litex/soc/cores/cpu/minerva/core.py | 1 + litex/soc/cores/cpu/mor1kx/core.py | 1 + litex/soc/cores/cpu/picorv32/core.py | 1 + litex/soc/cores/cpu/rocket/core.py | 1 + litex/soc/cores/cpu/serv/core.py | 1 + litex/soc/cores/cpu/vexriscv/core.py | 1 + litex/soc/integration/soc.py | 6 ++++-- litex/soc/software/bios/sdram.c | 25 +------------------------ 11 files changed, 14 insertions(+), 26 deletions(-) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 03690eb8..302aa70d 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -53,6 +53,7 @@ class BlackParrotRV64(CPU): gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf64-littleriscv" + nop = "nop" io_regions = {0x50000000: 0x10000000} # origin, length @property diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index f05329fa..2b6273f3 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -23,6 +23,7 @@ class LM32(CPU): endianness = "big" gcc_triple = "lm32-elf" linker_output_format = "elf32-lm32" + nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length @property diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 808ac0a7..76eb59dc 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -21,6 +21,7 @@ class Microwatt(CPU): endianness = "little" gcc_triple = ("powerpc64le-linux") linker_output_format = "elf64-powerpcle" + nop = "nop" io_regions = {0xc0000000: 0x10000000} # origin, length @property diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 524cd7f0..2a6f21f9 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -22,6 +22,7 @@ class Minerva(CPU): gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" + nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length @property diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 8e91dd94..5f05ef34 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -23,6 +23,7 @@ class MOR1KX(CPU): gcc_triple = "or1k-elf" clang_triple = "or1k-linux" linker_output_format = "elf32-or1k" + nop = "l.nop" io_regions = {0x80000000: 0x80000000} # origin, length @property diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 761a926e..b3bfc074 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -39,6 +39,7 @@ class PicoRV32(CPU): gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" + nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length @property diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index cac2b05b..e0100c76 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -72,6 +72,7 @@ class RocketRV64(CPU): gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf64-littleriscv" + nop = "nop" io_regions = {0x10000000: 0x70000000} # origin, length @property diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index ee31b348..dbb6a1b4 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -22,6 +22,7 @@ class SERV(CPU): gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" + nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length @property diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 990333bd..45fc0df9 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -82,6 +82,7 @@ class VexRiscv(CPU, AutoCSR): gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" + nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length @property diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 0256fc77..8d510762 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -793,9 +793,11 @@ class SoC(Module): self.comb += self.cpu.reset.eq(self.ctrl.reset) self.add_config("CPU_RESET_ADDR", reset_address) # Add constants - self.add_config("CPU_TYPE", str(name)) - self.add_config("CPU_VARIANT", str(variant.split('+')[0])) + self.add_config("CPU_TYPE", str(name)) + self.add_config("CPU_VARIANT", str(variant.split('+')[0])) self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown")) + if hasattr(self.cpu, "nop"): + self.add_constant("CONFIG_CPU_NOP", self.cpu.nop) def add_timer(self, name="timer0"): self.check_if_exists(name) diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c index 1e139d5d..1923b49b 100644 --- a/litex/soc/software/bios/sdram.c +++ b/litex/soc/software/bios/sdram.c @@ -29,31 +29,8 @@ __attribute__((unused)) static void cdelay(int i) { - /* FIXME: move nop definitions to CPUs */ while(i > 0) { -#if defined (__lm32__) - __asm__ volatile("nop"); -#elif defined (__or1k__) - __asm__ volatile("l.nop"); -#elif defined (__picorv32__) - __asm__ volatile("nop"); -#elif defined (__vexriscv__) - __asm__ volatile("nop"); -#elif defined (__minerva__) - __asm__ volatile("nop"); -#elif defined (__rocket__) - __asm__ volatile("nop"); -#elif defined (__powerpc__) - __asm__ volatile("nop"); -#elif defined (__microwatt__) - __asm__ volatile("nop"); -#elif defined (__blackparrot__) - __asm__ volatile("nop"); -#elif defined (__serv__) - __asm__ volatile("nop"); -#else -#error Unsupported architecture -#endif + __asm__ volatile(CONFIG_CPU_NOP); i--; } } -- 2.30.2