From 98060bbea842d8b0f3b5d41efa6ef15c266efcf4 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 27 Jul 2016 20:31:57 +0000 Subject: [PATCH] vector.md (vec_extract): Change the calling signature of rs6000_expand_vector_extract so that the... 2016-07-27 Michael Meissner * config/rs6000/vector.md (vec_extract): Change the calling signature of rs6000_expand_vector_extract so that the element number is a RTX instead of a constant integer. * config/rs6000/rs6000-protos.h (rs6000_expand_vector_extract): Likewise. * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Likewise. (altivec_expand_vec_ext_builtin): Likewise. * config/rs6000/altivec.md (reduc_plus_scal_): Likewise. * config/rs6000/vsx.md (vsx_extract_): Fix spelling of the MFVSRLD instruction. From-SVN: r238799 --- gcc/ChangeLog | 13 ++++++++++++ gcc/config/rs6000/altivec.md | 2 +- gcc/config/rs6000/rs6000-protos.h | 2 +- gcc/config/rs6000/rs6000.c | 33 +++++++++++++++++++------------ gcc/config/rs6000/vector.md | 3 +-- gcc/config/rs6000/vsx.md | 2 +- 6 files changed, 37 insertions(+), 18 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9e359bc1e69..858228fbb69 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2016-07-27 Michael Meissner + + * config/rs6000/vector.md (vec_extract): Change the calling + signature of rs6000_expand_vector_extract so that the element + number is a RTX instead of a constant integer. + * config/rs6000/rs6000-protos.h (rs6000_expand_vector_extract): + Likewise. + * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Likewise. + (altivec_expand_vec_ext_builtin): Likewise. + * config/rs6000/altivec.md (reduc_plus_scal_): Likewise. + * config/rs6000/vsx.md (vsx_extract_): Fix spelling of the + MFVSRLD instruction. + 2016-07-27 David Malcolm * input.c (get_pure_location): Move here from tree.c. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 9193f07e2f0..c39a0b655b4 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2781,7 +2781,7 @@ emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero)); emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); - rs6000_expand_vector_extract (operands[0], vtmp2, elt); + rs6000_expand_vector_extract (operands[0], vtmp2, GEN_INT (elt)); DONE; }) diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 0a47075d6bf..fefe7049804 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -61,7 +61,7 @@ extern void convert_int_to_float128 (rtx *, enum rtx_code); extern void rs6000_expand_vector_init (rtx, rtx); extern void paired_expand_vector_init (rtx, rtx); extern void rs6000_expand_vector_set (rtx, rtx, int); -extern void rs6000_expand_vector_extract (rtx, rtx, int); +extern void rs6000_expand_vector_extract (rtx, rtx, rtx); extern bool altivec_expand_vec_perm_const (rtx op[4]); extern void altivec_expand_vec_perm_le (rtx op[4]); extern bool rs6000_expand_vec_perm_const (rtx op[4]); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8a3e7994c95..ac331109bd2 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6911,35 +6911,35 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) /* Extract field ELT from VEC into TARGET. */ void -rs6000_expand_vector_extract (rtx target, rtx vec, int elt) +rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt) { machine_mode mode = GET_MODE (vec); machine_mode inner_mode = GET_MODE_INNER (mode); rtx mem; - if (VECTOR_MEM_VSX_P (mode)) + if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt)) { switch (mode) { default: break; case V1TImode: - gcc_assert (elt == 0 && inner_mode == TImode); + gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode); emit_move_insn (target, gen_lowpart (TImode, vec)); break; case V2DFmode: - emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt))); + emit_insn (gen_vsx_extract_v2df (target, vec, elt)); return; case V2DImode: - emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt))); + emit_insn (gen_vsx_extract_v2di (target, vec, elt)); return; case V4SFmode: - emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt))); + emit_insn (gen_vsx_extract_v4sf (target, vec, elt)); return; case V16QImode: if (TARGET_VEXTRACTUB) { - emit_insn (gen_vsx_extract_v16qi (target, vec, GEN_INT (elt))); + emit_insn (gen_vsx_extract_v16qi (target, vec, elt)); return; } else @@ -6947,7 +6947,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt) case V8HImode: if (TARGET_VEXTRACTUB) { - emit_insn (gen_vsx_extract_v8hi (target, vec, GEN_INT (elt))); + emit_insn (gen_vsx_extract_v8hi (target, vec, elt)); return; } else @@ -6955,7 +6955,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt) case V4SImode: if (TARGET_VEXTRACTUB) { - emit_insn (gen_vsx_extract_v4si (target, vec, GEN_INT (elt))); + emit_insn (gen_vsx_extract_v4si (target, vec, elt)); return; } else @@ -6963,13 +6963,16 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt) } } + gcc_assert (CONST_INT_P (elt)); + /* Allocate mode-sized buffer. */ mem = assign_stack_temp (mode, GET_MODE_SIZE (mode)); emit_move_insn (mem, vec); /* Add offset to field within buffer matching vector element. */ - mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode)); + mem = adjust_address_nv (mem, inner_mode, + INTVAL (elt) * GET_MODE_SIZE (inner_mode)); emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0)); } @@ -14658,14 +14661,18 @@ altivec_expand_vec_ext_builtin (tree exp, rtx target) { machine_mode tmode, mode0; tree arg0, arg1; - int elt; rtx op0; + rtx op1; arg0 = CALL_EXPR_ARG (exp, 0); arg1 = CALL_EXPR_ARG (exp, 1); op0 = expand_normal (arg0); - elt = get_element_number (TREE_TYPE (arg0), arg1); + op1 = expand_normal (arg1); + + /* Call get_element_number to validate arg1 if it is a constant. */ + if (TREE_CODE (arg1) == INTEGER_CST) + (void) get_element_number (TREE_TYPE (arg0), arg1); tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); mode0 = TYPE_MODE (TREE_TYPE (arg0)); @@ -14676,7 +14683,7 @@ altivec_expand_vec_ext_builtin (tree exp, rtx target) if (optimize || !target || !register_operand (target, tmode)) target = gen_reg_rtx (tmode); - rs6000_expand_vector_extract (target, op0, elt); + rs6000_expand_vector_extract (target, op0, op1); return target; } diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 51a91657d49..fbfa9bf12e4 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -858,8 +858,7 @@ (match_operand 2 "const_int_operand" "")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" { - rs6000_expand_vector_extract (operands[0], operands[1], - INTVAL (operands[2])); + rs6000_expand_vector_extract (operands[0], operands[1], operands[2]); DONE; }) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 861b1479a2e..1fddebcf5c3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2159,7 +2159,7 @@ else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno) && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE) - return "mfvsrdl %0,%x1"; + return "mfvsrld %0,%x1"; else if (VSX_REGNO_P (op0_regno)) { -- 2.30.2