From 980a83a74c6fd3c5e0edfe301636a5b3a6c50784 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 22 Sep 2013 11:45:30 +0200 Subject: [PATCH] move trigger/recorder --- examples/de0_nano/top.py | 12 +++++++----- miscope/{recording/__init__.py => storage.py} | 0 miscope/{triggering/__init__.py => trigger.py} | 0 sim/tb_recorder_csr.py | 5 ++--- sim/tb_trigger_csr.py | 5 ++--- 5 files changed, 11 insertions(+), 11 deletions(-) rename miscope/{recording/__init__.py => storage.py} (100%) rename miscope/{triggering/__init__.py => trigger.py} (100%) diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 04f14f03..4aca2af1 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -19,9 +19,11 @@ from migen.bus import csr from migen.bank import csrgen from miscope.std.misc import * -from miscope.triggering import * -from miscope.recording import * -from miscope import miio, mila + +from miscope.trigger import Term, Sum, Trigger +from miscope.storage import Recorder +from miscope.miio import MiIo +from miscope.mila import MiLa from miscope.com import uart2csr @@ -52,14 +54,14 @@ class SoC(Module): def __init__(self, platform): # MiIo - self.submodules.miio = miio.MiIo(8) + self.submodules.miio = MiIo(8) # MiLa term = Term(trig_w) trigger = Trigger(trig_w, [term]) recorder = Recorder(dat_w, rec_size) - self.submodules.mila = mila.MiLa(trigger, recorder) + self.submodules.mila = MiLa(trigger, recorder) # Uart2Csr self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200) diff --git a/miscope/recording/__init__.py b/miscope/storage.py similarity index 100% rename from miscope/recording/__init__.py rename to miscope/storage.py diff --git a/miscope/triggering/__init__.py b/miscope/trigger.py similarity index 100% rename from miscope/triggering/__init__.py rename to miscope/trigger.py diff --git a/sim/tb_recorder_csr.py b/sim/tb_recorder_csr.py index a14eba00..c4a98fd4 100644 --- a/sim/tb_recorder_csr.py +++ b/sim/tb_recorder_csr.py @@ -5,10 +5,9 @@ from migen.sim.generic import Simulator, TopLevel from migen.sim.icarus import Runner from migen.bus.transactions import * -from miscope.recording import * -from miscope.std.truthtable import * - from miscope.std import cif +from miscope.std.truthtable import * +from miscope.storage import * from mibuild.tools import write_to_file diff --git a/sim/tb_trigger_csr.py b/sim/tb_trigger_csr.py index d2be9214..f669ac84 100644 --- a/sim/tb_trigger_csr.py +++ b/sim/tb_trigger_csr.py @@ -5,10 +5,9 @@ from migen.sim.generic import Simulator, TopLevel from migen.sim.icarus import Runner from migen.bus.transactions import * -from miscope.triggering import * -from miscope.std.truthtable import * - from miscope.std import cif +from miscope.std.truthtable import * +from miscope.trigger import * from mibuild.tools import write_to_file -- 2.30.2