From 982f872763a71619167d4f204ef3fbc776476ac6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Dec 2021 19:08:32 +0000 Subject: [PATCH] add OP_FETCH_FAILED to MMU Function Unit --- src/soc/fu/mmu/fsm.py | 24 ++++++++++++++++++++++-- src/soc/fu/mmu/mmu_input_record.py | 2 +- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index a7930232..ae71f97b 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -26,6 +26,7 @@ from soc.experiment.mem_types import MMUToLoadStore1Type from soc.fu.ldst.loadstore import LoadStore1, TestSRAMLoadStore1 from nmutil.util import Display + class FSMMMUStage(ControlBase): """FSM MMU @@ -86,9 +87,10 @@ class FSMMMUStage(ControlBase): comb += ldst.m_in.eq(l_out) i_data, o_data = self.p.i_data, self.n.o_data - a_i, b_i, o, spr1_o = i_data.ra, i_data.rb, o_data.o, o_data.spr1 op = i_data.ctx.op - spr1_i = i_data.spr1 + nia_i = op.nia + a_i, b_i, spr1_i = i_data.ra, i_data.rb, i_data.spr1 + o, spr1_o = o_data.o, o_data.spr1 # busy/done signals busy = Signal() @@ -205,6 +207,24 @@ class FSMMMUStage(ControlBase): comb += done.eq(l_out.done) # zzzz comb += self.debug0.eq(2) + ########## + # OP_FETCH_FAILED + ########## + + with m.Case(MicrOp.OP_FETCH_FAILED): + comb += Display("MMUTEST: OP_FETCH_FAILED: @%x", nia_i) + # trigger an instruction fetch failed MMU event. + # PowerDecoder2 drops svstate.pc into NIA for us + # really, this should be direct communication with the + # MMU, rather than going through LoadStore1. but, doing + # so allows for the opportunity to prevent LoadStore1 + # from accepting any other LD/ST requests. + comb += valid.eq(1) # start "pulse" + comb += ldst.instr_fault.eq(blip) + comb += ldst.maddr.eq(nia_i) + comb += done.eq(ldst.done) # zzzz + comb += self.debug0.eq(3) + ############ # OP_ILLEGAL ############ diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py index 281e8dd8..079c2e9f 100644 --- a/src/soc/fu/mmu/mmu_input_record.py +++ b/src/soc/fu/mmu/mmu_input_record.py @@ -13,7 +13,7 @@ class CompMMUOpSubset(CompOpSubsetBase): layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), - ('cia', 64), # for instruction fault (MMU PTE lookup) + ('nia', 64), # for instruction fault (MMU PTE lookup) ('zero_a', 1), ) super().__init__(layout, name=name) -- 2.30.2