From 983fac08dac5067b9b5c725d261b8be5322e6bd6 Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 26 Jun 2022 18:46:14 +0300
Subject: [PATCH] ppc/svp64: support svindex instruction

---
 gas/testsuite/gas/ppc/svindex.d | 16 ++++++++++++++++
 gas/testsuite/gas/ppc/svindex.s |  8 ++++++++
 opcodes/ppc-opc.c               | 14 ++++++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/ppc/svindex.d
 create mode 100644 gas/testsuite/gas/ppc/svindex.s

diff --git a/gas/testsuite/gas/ppc/svindex.d b/gas/testsuite/gas/ppc/svindex.d
new file mode 100644
index 00000000000..73bda732870
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:	(29 00 00 58|58 00 00 29) 	svindex r0,0,1,0,0,0,0
+.*:	(29 00 e0 5b|5b e0 00 29) 	svindex r31,0,1,0,0,0,0
+.*:	(29 00 1f 58|58 1f 00 29) 	svindex r0,31,1,0,0,0,0
+.*:	(29 f8 00 58|58 00 f8 29) 	svindex r0,0,32,0,0,0,0
+.*:	(29 06 00 58|58 00 06 29) 	svindex r0,0,1,3,0,0,0
+.*:	(29 01 00 58|58 00 01 29) 	svindex r0,0,1,0,1,0,0
+.*:	(a9 00 00 58|58 00 00 a9) 	svindex r0,0,1,0,0,1,0
+.*:	(69 00 00 58|58 00 00 69) 	svindex r0,0,1,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/svindex.s b/gas/testsuite/gas/ppc/svindex.s
new file mode 100644
index 00000000000..ab256c433b2
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svindex.s
@@ -0,0 +1,8 @@
+svindex 0,0,1,0,0,0,0
+svindex 31,0,1,0,0,0,0
+svindex 0,31,1,0,0,0,0
+svindex 0,0,32,0,0,0,0
+svindex 0,0,1,3,0,0,0
+svindex 0,0,1,0,1,0,0
+svindex 0,0,1,0,0,1,0
+svindex 0,0,1,0,0,0,1
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a27796b7ba7..0d46cd0b3c6 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3557,6 +3557,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The UIMM field in a VX form instruction.  */
 #define UIMM SIMM + 1
 #define DCTL UIMM
+#define rmm UIMM
   { 0x1f, 16, NULL, NULL, 0 },
 
   /* The 3-bit UIMM field in a VX form instruction.  */
@@ -3649,6 +3650,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The RMC or CY field in a Z23 form instruction.  */
 #define RMC A_L + 1
 #define CY RMC
+#define ew RMC
   { 0x3, 9, NULL, NULL, 0 },
 
 #define R RMC + 1
@@ -3837,12 +3839,15 @@ const struct powerpc_operand powerpc_operands[] =
   { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
 
 #define vf SVi + 1
+#define sk vf
   { 0x1, 6, NULL, NULL, 0 },
 
 #define vs vf + 1
+#define mm vs
   { 0x1, 7, NULL, NULL, 0 },
 
 #define ms vs + 1
+#define yx ms
   { 0x1, 8, NULL, NULL, 0 },
 
 #define SVLcr ms + 1
@@ -3855,6 +3860,7 @@ const struct powerpc_operand powerpc_operands[] =
   { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
 
 #define SVzd SVyd + 1
+#define SVd SVzd
   { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
 
 #define SVRMf SVzd + 1
@@ -4753,6 +4759,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
    | (((uint64_t)(xop)) & 0x3f))
 #define SVRM_MASK	SVRM (0x3f, 0x3f)
 
+/* An SVI form instruction. */
+#define SVI(op, xop)				\
+  (OP (op)					\
+   | (((uint64_t)(xop)) & 0x3f))
+#define SVI_MASK	SVI (0x3f, 0x3f)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -6830,6 +6842,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
 {"setvl.",	SVL(22,27,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
 
+{"svindex",	SVI(22,41),	SVI_MASK,	SVP64,	PPCVLE,	{RS, rmm, SVd, ew, yx, mm, sk}},
+
 {"svremap",	SVRM(22,57),	SVRM_MASK,	SVP64,	PPCVLE,	{SVme, mi0, mi1, mi2, mo0, mo1, pst}},
 
 {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
-- 
2.30.2