From 987ba558b088748ac74034b0fbf09d0900db39bd Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 31 Oct 2001 04:08:19 +0000 Subject: [PATCH] elf.h: Fix comment formatting. * config/elf.h: Fix comment formatting. * config/elf64.h: Likewise. * config/iris5.h: Likewise. * config/iris5gas.h: Likewise. * config/iris6.h: Likewise. * config/isa3264.h: Likewise. * config/linux.h: Likewise. * config/mips.c: Likewise. * config/mips.h: Likewise. * config/mips.md: Likewise. * config/mips16.S: Likewise. * config/netbsd.h: Likewise. * config/osfrose.h: Likewise. * config/r3900.h: Likewise. * config/sni-svr4.h: Likewise. * config/svr4-t.h: Likewise. * config/ultrix.h: Likewise. From-SVN: r46670 --- gcc/ChangeLog | 20 ++++++++++ gcc/config/mips/elf.h | 4 +- gcc/config/mips/elf64.h | 2 +- gcc/config/mips/iris5.h | 4 +- gcc/config/mips/iris5gas.h | 2 +- gcc/config/mips/iris6.h | 4 +- gcc/config/mips/isa3264.h | 4 +- gcc/config/mips/linux.h | 4 +- gcc/config/mips/mips.c | 76 +++++++++++++++++++------------------- gcc/config/mips/mips.h | 54 +++++++++++++-------------- gcc/config/mips/mips.md | 2 +- gcc/config/mips/mips16.S | 2 +- gcc/config/mips/netbsd.h | 2 +- gcc/config/mips/osfrose.h | 2 +- gcc/config/mips/r3900.h | 4 +- gcc/config/mips/sni-svr4.h | 2 +- gcc/config/mips/svr4-t.h | 2 +- gcc/config/mips/ultrix.h | 2 +- 18 files changed, 106 insertions(+), 86 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f2c0b5b838..0dc6a4ba024 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2001-10-30 Kazu Hirata + + * config/elf.h: Fix comment formatting. + * config/elf64.h: Likewise. + * config/iris5.h: Likewise. + * config/iris5gas.h: Likewise. + * config/iris6.h: Likewise. + * config/isa3264.h: Likewise. + * config/linux.h: Likewise. + * config/mips.c: Likewise. + * config/mips.h: Likewise. + * config/mips.md: Likewise. + * config/mips16.S: Likewise. + * config/netbsd.h: Likewise. + * config/osfrose.h: Likewise. + * config/r3900.h: Likewise. + * config/sni-svr4.h: Likewise. + * config/svr4-t.h: Likewise. + * config/ultrix.h: Likewise. + 2001-10-30 Daniel Berlin * bitmap.c (bitmap_element_free): Don't forget to update head->indx diff --git a/gcc/config/mips/elf.h b/gcc/config/mips/elf.h index ef942179e70..f07b5a72d20 100644 --- a/gcc/config/mips/elf.h +++ b/gcc/config/mips/elf.h @@ -114,7 +114,7 @@ do { \ specified as the number of bits. Try to use function `asm_output_aligned_bss' defined in file - `varasm.c' when defining this macro. */ + `varasm.c' when defining this macro. */ #ifndef ASM_OUTPUT_ALIGNED_BSS #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ do { \ @@ -194,7 +194,7 @@ do { \ mips-elf gas supports .weak, but not .weakext. mips-elf gas has been changed to support both .weak and .weakext, but until that support is generally available, the 'if' below - should serve. */ + should serve. */ #undef ASM_WEAKEN_LABEL #define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) diff --git a/gcc/config/mips/elf64.h b/gcc/config/mips/elf64.h index cc94020e804..0317fde5380 100644 --- a/gcc/config/mips/elf64.h +++ b/gcc/config/mips/elf64.h @@ -173,7 +173,7 @@ do { \ mips-elf gas supports .weak, but not .weakext. mips-elf gas has been changed to support both .weak and .weakext, but until that support is generally available, the 'if' below - should serve. */ + should serve. */ #undef ASM_WEAKEN_LABEL #define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) diff --git a/gcc/config/mips/iris5.h b/gcc/config/mips/iris5.h index eab210f9d44..7e3efa0a1f3 100644 --- a/gcc/config/mips/iris5.h +++ b/gcc/config/mips/iris5.h @@ -114,7 +114,7 @@ Boston, MA 02111-1307, USA. */ /* We do not want to run mips-tfile! */ #undef ASM_FINAL_SPEC -/* The system header files are C++ aware. */ +/* The system header files are C++ aware. */ /* ??? Unfortunately, most but not all of the headers are C++ aware. Specifically, curses.h is not, and as a consequence, defining this used to prevent libg++ building. This is no longer the case so @@ -123,7 +123,7 @@ Boston, MA 02111-1307, USA. */ fixing. */ #define NO_IMPLICIT_EXTERN_C 1 -/* We don't support debugging info for now. */ +/* We don't support debugging info for now. */ #undef DBX_DEBUGGING_INFO #undef SDB_DEBUGGING_INFO #undef MIPS_DEBUGGING_INFO diff --git a/gcc/config/mips/iris5gas.h b/gcc/config/mips/iris5gas.h index 477a55fb647..84922c1c163 100644 --- a/gcc/config/mips/iris5gas.h +++ b/gcc/config/mips/iris5gas.h @@ -1,4 +1,4 @@ -/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */ +/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */ /* Enable debugging. */ #define DBX_DEBUGGING_INFO diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h index 3ba80d2e634..d7a989ad007 100644 --- a/gcc/config/mips/iris6.h +++ b/gcc/config/mips/iris6.h @@ -131,7 +131,7 @@ Boston, MA 02111-1307, USA. */ #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG /* Force the generation of dwarf .debug_frame sections even if not - compiling -g. This guarantees that we can unwind the stack. */ + compiling -g. This guarantees that we can unwind the stack. */ #define DWARF2_FRAME_INFO 1 /* The size in bytes of a DWARF field indicating an offset or length @@ -228,7 +228,7 @@ Boston, MA 02111-1307, USA. */ #define SUBTARGET_ASM_SPEC "%{!mabi*:-n32} %{!mips*: %{!mabi*:-mips3} %{mabi=n32:-mips3} %{mabi=64:-mips4}}" /* Must pass -g0 to the assembler, otherwise it may overwrite our - debug info with its own debug info. */ + debug info with its own debug info. */ /* Must pass -show instead of -v. */ /* Must pass -G 0 to the assembler, otherwise we may get warnings about GOT overflow. */ diff --git a/gcc/config/mips/isa3264.h b/gcc/config/mips/isa3264.h index 61686445072..cde72272eba 100644 --- a/gcc/config/mips/isa3264.h +++ b/gcc/config/mips/isa3264.h @@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA. */ #include "mips/elf.h" /* This must be done after including mips.h so that the - ABI_{EABI,O64,O32,...} are #defined. */ + ABI_{EABI,O64,O32,...} are #defined. */ #if MIPS_ABI_DEFAULT == ABI_EABI #undef SUBTARGET_CPP_SIZE_SPEC @@ -110,7 +110,7 @@ Boston, MA 02111-1307, USA. */ For MEABI the size of longs is always 32bits. If long64 is specified then we honor that. The errors for long64 & long32 is because while CC1 can - handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */ + handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */ #if MIPS_ISA_DEFAULT == 3 || MIPS_ISA_DEFAULT == 4 || MIPS_ISA_DEFAULT == 5 || MIPS_ISA_DEFAULT == 64 #undef SUBTARGET_CPP_SIZE_SPEC diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h index 91f15102725..5b3c59649f2 100644 --- a/gcc/config/mips/linux.h +++ b/gcc/config/mips/linux.h @@ -47,7 +47,7 @@ Boston, MA 02111-1307, USA. */ specified as the number of bits. Try to use function `asm_output_aligned_bss' defined in file - `varasm.c' when defining this macro. */ + `varasm.c' when defining this macro. */ #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ do { \ ASM_GLOBALIZE_LABEL (FILE, NAME); \ @@ -149,7 +149,7 @@ void FN () \ /* Required to keep collect2.c happy */ #undef OBJECT_FORMAT_COFF -/* If we don't set MASK_ABICALLS, we can't default to PIC. */ +/* If we don't set MASK_ABICALLS, we can't default to PIC. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 88d7751f959..db1652984de 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -64,7 +64,7 @@ extern tree lookup_name PARAMS ((tree)); /* Enumeration for all of the relational tests, so that we can build arrays indexed by the test type, and not worry about the order - of EQ, NE, etc. */ + of EQ, NE, etc. */ enum internal_test { ITEST_EQ, @@ -145,7 +145,7 @@ int num_source_filenames = 0; start and end boundaries). */ int sdb_label_count = 0; -/* Next label # for each statement for Silicon Graphics IRIS systems. */ +/* Next label # for each statement for Silicon Graphics IRIS systems. */ int sym_lineno = 0; /* Non-zero if inside of a function, because the stupid MIPS asm can't @@ -248,7 +248,7 @@ const char *mips_no_mips16_string; /* This is only used to determine if an type size setting option was explicitly specified (-mlong64, -mint64, -mlong32). The specs - set this option if such an option is used. */ + set this option if such an option is used. */ const char *mips_explicit_type_size_string; /* Whether we are generating mips16 hard float code. In mips16 mode @@ -582,7 +582,7 @@ reg_or_0_operand (op, mode) } /* Return truth value of whether OP is a register or the constant 0, - even in mips16 mode. */ + even in mips16 mode. */ int true_reg_or_0_operand (op, mode) @@ -797,7 +797,7 @@ simple_memory_operand (op, mode) if (GET_CODE (op) != SYMBOL_REF) return 0; - /* let's be paranoid.... */ + /* let's be paranoid.... */ if (! SMALL_INT (offset)) return 0; } @@ -902,7 +902,7 @@ double_memory_operand (op, mode) return 1; /* Similarly, we accept a case where the memory address is - itself on the stack, and will be reloaded. */ + itself on the stack, and will be reloaded. */ if (GET_CODE (addr) == MEM) { rtx maddr; @@ -1294,7 +1294,7 @@ mips_legitimate_address_p (mode, xinsn, strict) } /* Check for constant before stripping off SUBREG, so that we don't - accept (subreg (const_int)) which will fail to reload. */ + accept (subreg (const_int)) which will fail to reload. */ if (CONSTANT_ADDRESS_P (xinsn) && ! (mips_split_addresses && mips_check_split (xinsn, mode)) && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0))) @@ -2729,7 +2729,7 @@ mips_address_cost (addr) return 2; } - /* ... fall through ... */ + /* ... fall through ... */ case SYMBOL_REF: return SYMBOL_REF_FLAG (addr) ? 1 : 2; @@ -3482,7 +3482,7 @@ expand_block_move (operands) The block move type can be one of the following: BLOCK_MOVE_NORMAL Do all of the block move. BLOCK_MOVE_NOT_LAST Do all but the last store. - BLOCK_MOVE_LAST Do just the last store. */ + BLOCK_MOVE_LAST Do just the last store. */ const char * output_block_move (insn, operands, num_regs, move_type) @@ -3859,7 +3859,7 @@ init_cumulative_args (cum, fntype, libname) /* Determine if this function has variable arguments. This is indicated by the last argument being 'void_type_mode' if there are no variable arguments. The standard MIPS calling sequence - passes all arguments in the general purpose registers in this case. */ + passes all arguments in the general purpose registers in this case. */ for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0; param != 0; param = next_param) @@ -4288,7 +4288,7 @@ function_arg_partial_nregs (cum, mode, type, named) Note that the GPR save area is not constant size, due to optimization in the prologue. Hence, we can't use a design with two pointers and two offsets, although we could have designed this with two pointers - and three offsets. */ + and three offsets. */ tree @@ -4351,7 +4351,7 @@ mips_va_start (stdarg_p, valist, nextarg) if (mips_abi == ABI_EABI) { int gpr_save_area_size; - /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */ + /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */ if (int_arg_words < 8 ) /* Adjust for the prologue's economy measure */ gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD; @@ -4387,7 +4387,7 @@ mips_va_start (stdarg_p, valist, nextarg) /* Emit code setting a pointer into the overflow (shared-stack) area. If there were more than 8 non-float formals, or more than 8 float formals, then this pointer isn't to the base of the area. - In that case, it must point to where the first vararg is. */ + In that case, it must point to where the first vararg is. */ size_excess = 0; if (float_formals > floats_passed_in_regs) size_excess += (float_formals-floats_passed_in_regs) * 8; @@ -4401,7 +4401,7 @@ mips_va_start (stdarg_p, valist, nextarg) take into account the exact sequence of floats and non-floats which make up the excess. That calculation should be rolled into the code which sets the current_function_args_info struct. - The above then reduces to a fetch from that struct. */ + The above then reduces to a fetch from that struct. */ t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); @@ -4411,7 +4411,7 @@ mips_va_start (stdarg_p, valist, nextarg) t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); - /* Emit code setting a ptr to the base of the overflow area. */ + /* Emit code setting a ptr to the base of the overflow area. */ t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); @@ -4421,7 +4421,7 @@ mips_va_start (stdarg_p, valist, nextarg) If mips4, this is gpr_save_area_size below the overflow area. If mips2, also round down to an 8-byte boundary, since the FPR save area is 8-byte aligned, and GPR is 4-byte-aligned. - Therefore there can be a 4-byte gap between the save areas. */ + Therefore there can be a 4-byte gap between the save areas. */ gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); fpr_save_offset = gpr_save_area_size; if (!TARGET_64BIT) @@ -4463,7 +4463,7 @@ mips_va_start (stdarg_p, valist, nextarg) /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */ /* Everything is in the GPR save area, or in the overflow - area which is contiguous with it. */ + area which is contiguous with it. */ int offset = -gpr_save_area_size; if (gpr_save_area_size == 0) @@ -4530,7 +4530,7 @@ mips_va_arg (valist, type) if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) { /* Case of all args in a merged stack. No need to check bounds, - just advance valist along the stack. */ + just advance valist along the stack. */ tree gpr = valist; if (! indirect @@ -4568,7 +4568,7 @@ mips_va_arg (valist, type) return addr_rtx; } - /* Not a simple merged stack. Need ptrs and indexes left by va_start. */ + /* Not a simple merged stack. Need ptrs and indexes left by va_start. */ f_ovfl = TYPE_FIELDS (va_list_type_node); f_gtop = TREE_CHAIN (f_ovfl); @@ -4588,7 +4588,7 @@ mips_va_arg (valist, type) if (TREE_CODE (type) == REAL_TYPE) { - /* Emit code to branch if foff == 0. */ + /* Emit code to branch if foff == 0. */ r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)), EXPAND_NORMAL); emit_cmp_and_jump_insns (r, const0_rtx, EQ, @@ -4616,7 +4616,7 @@ mips_va_arg (valist, type) /* For mips2, the overflow area contains mixed size items. If a 4-byte int is followed by an 8-byte float, then natural alignment causes a 4 byte gap. - So, dynamically adjust ovfl up to a multiple of 8. */ + So, dynamically adjust ovfl up to a multiple of 8. */ t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl, build_int_2 (7, 0)); t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t); @@ -4625,7 +4625,7 @@ mips_va_arg (valist, type) } /* Emit code for addr_rtx = the ovfl pointer into overflow area. - Regardless of mips2, postincrement the ovfl pointer by 8. */ + Regardless of mips2, postincrement the ovfl pointer by 8. */ t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl, size_int (8)); r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); @@ -4648,33 +4648,33 @@ mips_va_arg (valist, type) /* In mips2, int takes 32 bits of the GPR save area, but longlong takes an aligned 64 bits. So, emit code to zero the low order bits of goff, thus aligning - the later calculation of (gtop-goff) upwards. */ + the later calculation of (gtop-goff) upwards. */ t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff, build_int_2 (-8, -1)); t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t); expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); } - /* Emit code to branch if goff == 0. */ + /* Emit code to branch if goff == 0. */ r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)), EXPAND_NORMAL); emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r), 1, 1, lab_false); - /* Emit code for addr_rtx = gtop - goff. */ + /* Emit code for addr_rtx = gtop - goff. */ t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff); r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); if (r != addr_rtx) emit_move_insn (addr_rtx, r); - /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */ + /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */ if (! TARGET_64BIT && TYPE_PRECISION (type) == 64) step_size = 8; else step_size = UNITS_PER_WORD; /* Emit code for goff = goff - step_size. - Advances the offset up GPR save area over the item. */ + Advances the offset up GPR save area over the item. */ t = build (MINUS_EXPR, TREE_TYPE (goff), goff, build_int_2 (step_size, 0)); t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t); @@ -4711,7 +4711,7 @@ mips_va_arg (valist, type) } else { - /* Not EABI. */ + /* Not EABI. */ int align; /* ??? The original va-mips.h did always align, despite the fact @@ -4769,7 +4769,7 @@ override_options () /* If both single-float and soft-float are set, then clear the one that was set by TARGET_DEFAULT, leaving the one that was set by the user. We assume here that the specs prevent both being set by the - user. */ + user. */ #ifdef TARGET_DEFAULT if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT) target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT)); @@ -4815,7 +4815,7 @@ override_options () } #ifdef MIPS_ABI_DEFAULT - /* Get the ABI to use. */ + /* Get the ABI to use. */ if (mips_abi_string == (char *) 0) mips_abi = MIPS_ABI_DEFAULT; else if (! strcmp (mips_abi_string, "32")) @@ -7017,7 +7017,7 @@ mips_output_function_prologue (file, size) /* Require: OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg. - HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */ + HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */ } if (mips_entry && ! mips_can_use_return_insn ()) @@ -7194,7 +7194,7 @@ mips_expand_prologue () the varargs special argument, and treat it as part of the variable arguments. - This is only needed if store_args_on_stack is true. */ + This is only needed if store_args_on_stack is true. */ INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0); regno = GP_ARG_FIRST; @@ -7297,7 +7297,7 @@ mips_expand_prologue () int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD; rtx ptr = stack_pointer_rtx; - /* If we are doing svr4-abi, sp has already been decremented by tsize. */ + /* If we are doing svr4-abi, sp has already been decremented by tsize. */ if (TARGET_ABICALLS) offset += tsize; @@ -7515,7 +7515,7 @@ mips_expand_prologue () } /* Do any necessary cleanup after a function to restore stack, frame, - and regs. */ + and regs. */ #define RA_MASK BITMASK_HIGH /* 1 << 31 */ #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) @@ -8055,7 +8055,7 @@ function_arg_pass_by_reference (cum, mode, type, named) { /* Don't pass the actual CUM to FUNCTION_ARG, because we would get double copies of any offsets generated for small structs - passed in registers. */ + passed in registers. */ CUMULATIVE_ARGS temp; temp = *cum; if (FUNCTION_ARG (temp, mode, type, named) != 0) @@ -8808,7 +8808,7 @@ build_mips16_call_stub (retval, fnmem, arg_size, fp_code) /* We build the stub code by hand. That's the only way we can do it, since we can't generate 32 bit code during a 16 bit - compilation. */ + compilation. */ /* We don't want the assembler to insert any nops here. */ fprintf (asm_out_file, "\t.set\tnoreorder\n"); @@ -9476,7 +9476,7 @@ machine_dependent_reorg (first) { /* If we haven't had a barrier within 0x8000 bytes of a constant reference or we are at the end of the function, - emit a barrier now. */ + emit a barrier now. */ rtx label, jump, barrier; @@ -9621,7 +9621,7 @@ mips_output_conditional_branch (insn, break; case LTU: - /* A condition which will always be false. */ + /* A condition which will always be false. */ code = NE; op1 = "%."; break; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 88a23e153f9..f65789d2b49 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -80,7 +80,7 @@ enum processor_type { value at preprocessing time. ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all - defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */ + defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */ #define ABI_32 0 #define ABI_N32 1 @@ -96,7 +96,7 @@ enum processor_type { Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus' EABI the legacy EABI. In the end we may end up calling both ABI's EABI but give them different version numbers, but for now I'm going - with different names. */ + with different names. */ #define ABI_MEABI 5 @@ -127,7 +127,7 @@ enum block_move_type { BLOCK_MOVE_LAST /* generate just the last store */ }; -extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ +extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ extern char mips_print_operand_punct[]; /* print_operand punctuation chars */ extern const char *current_function_file; /* filename current function is in */ extern int num_source_filenames; /* current .file # */ @@ -245,7 +245,7 @@ extern void sbss_section PARAMS ((void)); #define MASK_DEBUG 0 /* unused */ #define MASK_DEBUG_A 0 /* don't allow