From 988464160305906f82723e32a076742e3f1ef0c4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 20 Jan 2020 01:17:32 -0800 Subject: [PATCH] base,arch,sim,cpu: Move object file loader components into a namespace. The components in base/loader were moved into a namespace called Loader. This will make it easier to add loader components with fairly short natural names which don't invite name collisions. gem5 should use namespaces more in general for that reason and to make it easier to write independent components without having to worry about name collisions being added in the future. Unfortunately this namespace has the same name as a class used to load an object file into a process object. These names can be disambiguated because the Process loader is inside the Process scope and the Loader namespace is at global scope, but it's still confusing to read. Fortunately, this shouldn't last for very long since the responsibility for loading Processes is going to move to a fake OS object which will expect to load a particular type of Process, for instance, fake 64 bit x86 linux will load either 32 or 64 bit x86 processes. That means that the capability to feed any binary that matches the current build into gem5 and have gem5 figure out what to do with it will likely be going away in the future. That's likely for the best, since it will force users to be more explicit about what they're trying to do, ie what OS they want to try to load a given binary, and also will prevent loading two or more Processes which are for different OSes to the same system, something that's possible today as far as I know since there are no consistency checks. Change-Id: Iea0012e98f39f5e20a7c351b78cdff9401f5e326 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24783 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/freebsd/fs_workload.cc | 5 +- src/arch/arm/freebsd/process.cc | 14 +- src/arch/arm/freebsd/process.hh | 8 +- src/arch/arm/fs_workload.cc | 10 +- src/arch/arm/fs_workload.hh | 10 +- src/arch/arm/insts/branch.cc | 9 +- src/arch/arm/insts/branch.hh | 9 +- src/arch/arm/insts/branch64.cc | 20 +- src/arch/arm/insts/branch64.hh | 20 +- src/arch/arm/insts/data64.cc | 36 +- src/arch/arm/insts/data64.hh | 26 +- src/arch/arm/insts/macromem.cc | 24 +- src/arch/arm/insts/macromem.hh | 16 +- src/arch/arm/insts/mem.cc | 4 +- src/arch/arm/insts/mem.hh | 10 +- src/arch/arm/insts/mem64.cc | 29 +- src/arch/arm/insts/mem64.hh | 20 +- src/arch/arm/insts/misc.cc | 59 +-- src/arch/arm/insts/misc.hh | 44 +- src/arch/arm/insts/misc64.cc | 21 +- src/arch/arm/insts/misc64.hh | 16 +- src/arch/arm/insts/pred_inst.cc | 18 +- src/arch/arm/insts/pred_inst.hh | 12 +- src/arch/arm/insts/pseudo.cc | 9 +- src/arch/arm/insts/pseudo.hh | 6 +- src/arch/arm/insts/static_inst.cc | 6 +- src/arch/arm/insts/static_inst.hh | 6 +- src/arch/arm/insts/sve.cc | 178 ++++---- src/arch/arm/insts/sve.hh | 150 ++++--- src/arch/arm/insts/sve_macromem.hh | 12 +- src/arch/arm/insts/sve_mem.cc | 14 +- src/arch/arm/insts/sve_mem.hh | 12 +- src/arch/arm/insts/vfp.cc | 25 +- src/arch/arm/insts/vfp.hh | 18 +- src/arch/arm/isa/templates/sve_mem.isa | 16 +- src/arch/arm/linux/fs_workload.cc | 9 +- src/arch/arm/linux/process.cc | 20 +- src/arch/arm/linux/process.hh | 8 +- src/arch/arm/process.cc | 21 +- src/arch/arm/process.hh | 16 +- src/arch/arm/stacktrace.cc | 2 +- src/arch/arm/system.cc | 2 +- src/arch/mips/isa/base.isa | 12 +- src/arch/mips/isa/formats/branch.isa | 17 +- src/arch/mips/isa/formats/control.isa | 224 +++++----- src/arch/mips/isa/formats/fp.isa | 307 +++++++------- src/arch/mips/isa/formats/int.isa | 455 ++++++++++----------- src/arch/mips/isa/formats/mem.isa | 17 +- src/arch/mips/isa/formats/mt.isa | 48 +-- src/arch/mips/isa/formats/noop.isa | 6 +- src/arch/mips/isa/formats/tlbop.isa | 64 ++- src/arch/mips/isa/formats/trap.isa | 120 +++--- src/arch/mips/isa/formats/unimp.isa | 30 +- src/arch/mips/isa/formats/unknown.isa | 5 +- src/arch/mips/linux/process.cc | 12 +- src/arch/mips/linux/process.hh | 2 +- src/arch/mips/process.cc | 4 +- src/arch/mips/process.hh | 5 +- src/arch/power/insts/branch.cc | 20 +- src/arch/power/insts/branch.hh | 14 +- src/arch/power/insts/condition.cc | 6 +- src/arch/power/insts/condition.hh | 4 +- src/arch/power/insts/floating.cc | 2 +- src/arch/power/insts/floating.hh | 2 +- src/arch/power/insts/integer.cc | 10 +- src/arch/power/insts/integer.hh | 8 +- src/arch/power/insts/mem.cc | 5 +- src/arch/power/insts/mem.hh | 4 +- src/arch/power/insts/misc.cc | 2 +- src/arch/power/insts/misc.hh | 9 +- src/arch/power/insts/static_inst.cc | 4 +- src/arch/power/insts/static_inst.hh | 2 +- src/arch/power/isa/formats/unimp.isa | 12 +- src/arch/power/isa/formats/unknown.isa | 5 +- src/arch/power/linux/process.cc | 12 +- src/arch/power/linux/process.hh | 2 +- src/arch/power/process.cc | 5 +- src/arch/power/process.hh | 5 +- src/arch/riscv/bare_metal/fs_workload.cc | 4 +- src/arch/riscv/bare_metal/fs_workload.hh | 12 +- src/arch/riscv/insts/amo.cc | 35 +- src/arch/riscv/insts/amo.hh | 14 +- src/arch/riscv/insts/compressed.cc | 3 +- src/arch/riscv/insts/compressed.hh | 2 +- src/arch/riscv/insts/mem.cc | 4 +- src/arch/riscv/insts/mem.hh | 4 +- src/arch/riscv/insts/pseudo.hh | 4 +- src/arch/riscv/insts/standard.cc | 4 +- src/arch/riscv/insts/standard.hh | 7 +- src/arch/riscv/insts/unknown.hh | 3 +- src/arch/riscv/isa/formats/compressed.isa | 8 +- src/arch/riscv/isa/formats/standard.isa | 22 +- src/arch/riscv/linux/process.cc | 16 +- src/arch/riscv/linux/process.hh | 4 +- src/arch/riscv/process.cc | 11 +- src/arch/riscv/process.hh | 10 +- src/arch/sparc/fs_workload.hh | 6 +- src/arch/sparc/insts/blockmem.cc | 6 +- src/arch/sparc/insts/blockmem.hh | 4 +- src/arch/sparc/insts/branch.cc | 8 +- src/arch/sparc/insts/branch.hh | 6 +- src/arch/sparc/insts/integer.cc | 10 +- src/arch/sparc/insts/integer.hh | 10 +- src/arch/sparc/insts/mem.cc | 4 +- src/arch/sparc/insts/mem.hh | 4 +- src/arch/sparc/insts/micro.cc | 3 +- src/arch/sparc/insts/micro.hh | 2 +- src/arch/sparc/insts/nop.cc | 7 +- src/arch/sparc/insts/nop.hh | 3 +- src/arch/sparc/insts/priv.cc | 9 +- src/arch/sparc/insts/priv.hh | 8 +- src/arch/sparc/insts/static_inst.cc | 3 +- src/arch/sparc/insts/static_inst.hh | 2 +- src/arch/sparc/insts/trap.cc | 2 +- src/arch/sparc/insts/trap.hh | 5 +- src/arch/sparc/insts/unimp.hh | 6 +- src/arch/sparc/insts/unknown.hh | 3 +- src/arch/sparc/linux/process.cc | 16 +- src/arch/sparc/linux/process.hh | 4 +- src/arch/sparc/process.cc | 6 +- src/arch/sparc/process.hh | 6 +- src/arch/sparc/solaris/process.cc | 12 +- src/arch/sparc/solaris/process.hh | 2 +- src/arch/x86/faults.cc | 3 +- src/arch/x86/fs_workload.cc | 2 +- src/arch/x86/insts/macroop.hh | 2 +- src/arch/x86/insts/microfpop.cc | 5 +- src/arch/x86/insts/microfpop.hh | 4 +- src/arch/x86/insts/microldstop.cc | 10 +- src/arch/x86/insts/microldstop.hh | 8 +- src/arch/x86/insts/micromediaop.cc | 10 +- src/arch/x86/insts/micromediaop.hh | 4 +- src/arch/x86/insts/microop.hh | 4 +- src/arch/x86/insts/microregop.cc | 10 +- src/arch/x86/insts/microregop.hh | 8 +- src/arch/x86/insts/static_inst.cc | 5 +- src/arch/x86/insts/static_inst.hh | 4 +- src/arch/x86/isa/formats/cpuid.isa | 7 +- src/arch/x86/isa/formats/monitor_mwait.isa | 14 +- src/arch/x86/isa/formats/nop.isa | 4 +- src/arch/x86/isa/formats/syscall.isa | 7 +- src/arch/x86/isa/formats/unimp.isa | 16 +- src/arch/x86/isa/formats/unknown.isa | 53 +-- src/arch/x86/isa/macroop.isa | 71 ++-- src/arch/x86/isa/microops/debug.isa | 2 +- src/arch/x86/isa/microops/limmop.isa | 7 +- src/arch/x86/isa/microops/seqop.isa | 7 +- src/arch/x86/isa/microops/specop.isa | 14 +- src/arch/x86/linux/process.cc | 12 +- src/arch/x86/process.cc | 14 +- src/arch/x86/process.hh | 6 +- src/arch/x86/stacktrace.cc | 4 +- src/base/cp_annotate.cc | 10 +- src/base/cp_annotate.hh | 2 +- src/base/loader/dtb_file.cc | 5 + src/base/loader/dtb_file.hh | 5 + src/base/loader/elf_object.cc | 5 + src/base/loader/elf_object.hh | 5 + src/base/loader/image_file.hh | 5 + src/base/loader/image_file_data.cc | 5 + src/base/loader/image_file_data.hh | 5 + src/base/loader/image_file_data.test.cc | 2 + src/base/loader/memory_image.cc | 5 + src/base/loader/memory_image.hh | 4 + src/base/loader/object_file.cc | 10 +- src/base/loader/object_file.hh | 55 +-- src/base/loader/raw_image.hh | 5 +- src/base/loader/symtab.cc | 5 + src/base/loader/symtab.hh | 5 + src/cpu/base.cc | 7 +- src/cpu/exetrace.cc | 7 +- src/cpu/profile.cc | 6 +- src/cpu/profile.hh | 6 +- src/cpu/static_inst.cc | 5 +- src/cpu/static_inst.hh | 14 +- src/kern/linux/helpers.cc | 2 +- src/mem/abstract_mem.cc | 6 +- src/python/pybind11/core.cc | 2 +- src/sim/kernel_workload.cc | 14 +- src/sim/kernel_workload.hh | 19 +- src/sim/process.cc | 28 +- src/sim/process.hh | 22 +- src/sim/pseudo_inst.cc | 2 +- src/sim/syscall_emul.hh | 4 +- src/sim/system.hh | 1 - src/sim/workload.hh | 10 +- src/unittest/nmtest.cc | 10 +- src/unittest/symtest.cc | 2 +- 188 files changed, 1801 insertions(+), 1576 deletions(-) diff --git a/src/arch/arm/freebsd/fs_workload.cc b/src/arch/arm/freebsd/fs_workload.cc index 4eff04d74..91a1d895c 100644 --- a/src/arch/arm/freebsd/fs_workload.cc +++ b/src/arch/arm/freebsd/fs_workload.cc @@ -82,7 +82,8 @@ FsFreebsd::initState() // it is helpful. if (params()->early_kernel_symbols) { kernelObj->loadGlobalSymbols(kernelSymtab, 0, 0, _loadAddrMask); - kernelObj->loadGlobalSymbols(debugSymbolTable, 0, 0, _loadAddrMask); + kernelObj->loadGlobalSymbols( + Loader::debugSymbolTable, 0, 0, _loadAddrMask); } // Check if the kernel image has a symbol that tells us it supports @@ -97,7 +98,7 @@ FsFreebsd::initState() inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename, params()->atags_addr + _loadAddrOffset); - DtbFile *dtb_file = new DtbFile(params()->dtb_filename); + auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename); warn_if(!dtb_file->addBootCmdLine(commandLine.c_str(), commandLine.size()), "Couldn't append bootargs to DTB file: %s", diff --git a/src/arch/arm/freebsd/process.cc b/src/arch/arm/freebsd/process.cc index 97ac77e2a..3955f85df 100644 --- a/src/arch/arm/freebsd/process.cc +++ b/src/arch/arm/freebsd/process.cc @@ -62,20 +62,20 @@ class ArmFreebsdObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { auto arch = obj_file->getArch(); auto opsys = obj_file->getOpSys(); - if (arch != ObjectFile::Arm && arch != ObjectFile::Thumb && - arch != ObjectFile::Arm64) { + if (arch != ::Loader::Arm && arch != ::Loader::Thumb && + arch != ::Loader::Arm64) { return nullptr; } - if (opsys != ObjectFile::FreeBSD) + if (opsys != ::Loader::FreeBSD) return nullptr; - if (arch == ObjectFile::Arm64) + if (arch == ::Loader::Arm64) return new ArmFreebsdProcess64(params, obj_file, arch); else return new ArmFreebsdProcess32(params, obj_file, arch); @@ -151,12 +151,12 @@ static SyscallDescTable syscallDescs64 = { }; ArmFreebsdProcess32::ArmFreebsdProcess32(ProcessParams * params, - ObjectFile *objFile, ObjectFile::Arch _arch) : + ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) : ArmProcess32(params, objFile, _arch) {} ArmFreebsdProcess64::ArmFreebsdProcess64(ProcessParams * params, - ObjectFile *objFile, ObjectFile::Arch _arch) : + ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) : ArmProcess64(params, objFile, _arch) {} diff --git a/src/arch/arm/freebsd/process.hh b/src/arch/arm/freebsd/process.hh index a972f17e8..ac0092e9f 100644 --- a/src/arch/arm/freebsd/process.hh +++ b/src/arch/arm/freebsd/process.hh @@ -77,8 +77,8 @@ struct Resultboot_loader.size()); for (const auto &bl : p->boot_loader) { - std::unique_ptr bl_obj; - bl_obj.reset(createObjectFile(bl)); + std::unique_ptr bl_obj; + bl_obj.reset(Loader::createObjectFile(bl)); fatal_if(!bl_obj, "Could not read bootloader: %s", bl); bootLoaders.emplace_back(std::move(bl_obj)); @@ -87,7 +87,7 @@ FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p), "Can't find a matching boot loader / kernel combination!"); if (bootldr) - bootldr->loadGlobalSymbols(debugSymbolTable); + bootldr->loadGlobalSymbols(Loader::debugSymbolTable); } void @@ -137,8 +137,8 @@ FsWorkload::initState() } } -ObjectFile * -FsWorkload::getBootLoader(ObjectFile *const obj) + Loader::ObjectFile * +FsWorkload::getBootLoader(Loader::ObjectFile *const obj) { if (obj) { for (auto &bl : bootLoaders) { diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh index 46694eb39..0618b8a9d 100644 --- a/src/arch/arm/fs_workload.hh +++ b/src/arch/arm/fs_workload.hh @@ -63,12 +63,12 @@ class FsWorkload : public KernelWorkload { protected: /** Bootloaders */ - std::vector> bootLoaders; + std::vector> bootLoaders; /** * Pointer to the bootloader object */ - ObjectFile *bootldr = nullptr; + Loader::ObjectFile *bootldr = nullptr; /** * This differs from entry since it takes into account where @@ -84,7 +84,7 @@ class FsWorkload : public KernelWorkload * @return Pointer to boot loader ObjectFile or nullptr if there * is no matching boot loader. */ - ObjectFile *getBootLoader(ObjectFile *const obj); + Loader::ObjectFile *getBootLoader(Loader::ObjectFile *const obj); public: typedef ArmFsWorkloadParams Params; @@ -103,7 +103,7 @@ class FsWorkload : public KernelWorkload return kernelEntry; } - ObjectFile::Arch + Loader::Arch getArch() const override { if (bootldr) @@ -111,7 +111,7 @@ class FsWorkload : public KernelWorkload else if (kernelObj) return kernelObj->getArch(); else - return ObjectFile::Arm64; + return Loader::Arm64; } FsWorkload(Params *p); diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc index c9f2ce7d7..053ad2ece 100644 --- a/src/arch/arm/insts/branch.cc +++ b/src/arch/arm/insts/branch.cc @@ -42,7 +42,8 @@ namespace ArmISA { std::string -BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchReg::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -51,7 +52,8 @@ BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchImm::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -60,7 +62,8 @@ BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -BranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchRegReg::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh index b7bdcb9ea..98c06fca5 100644 --- a/src/arch/arm/insts/branch.hh +++ b/src/arch/arm/insts/branch.hh @@ -57,7 +57,8 @@ class BranchImm : public PredOp PredOp(mnem, _machInst, __opClass), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; // Conditionally Branch to a target computed with an immediate @@ -86,7 +87,8 @@ class BranchReg : public PredOp PredOp(mnem, _machInst, __opClass), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; // Conditionally Branch to a target computed with a register @@ -116,7 +118,8 @@ class BranchRegReg : public PredOp PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; // Branch to a target computed with an immediate and a register diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc index dd57a1afa..2338f60d7 100644 --- a/src/arch/arm/insts/branch64.cc +++ b/src/arch/arm/insts/branch64.cc @@ -69,7 +69,7 @@ BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const std::string BranchImmCond64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false, true, condCode); @@ -79,7 +79,7 @@ BranchImmCond64::generateDisassembly( std::string BranchImm64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -89,7 +89,7 @@ BranchImm64::generateDisassembly( std::string BranchReg64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -99,7 +99,7 @@ BranchReg64::generateDisassembly( std::string BranchRegReg64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -111,7 +111,7 @@ BranchRegReg64::generateDisassembly( std::string BranchRet64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -122,7 +122,7 @@ BranchRet64::generateDisassembly( std::string BranchRetA64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -133,7 +133,7 @@ BranchRetA64::generateDisassembly( std::string BranchEret64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -142,7 +142,7 @@ BranchEret64::generateDisassembly( std::string BranchEretA64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -151,7 +151,7 @@ BranchEretA64::generateDisassembly( std::string BranchImmReg64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -163,7 +163,7 @@ BranchImmReg64::generateDisassembly( std::string BranchImmImmReg64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh index 59f93e13d..179326a1d 100644 --- a/src/arch/arm/insts/branch64.hh +++ b/src/arch/arm/insts/branch64.hh @@ -61,7 +61,7 @@ class BranchImm64 : public ArmStaticInst using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Conditionally Branch to a target computed with an immediate @@ -77,7 +77,7 @@ class BranchImmCond64 : public BranchImm64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Branch to a target computed with two registers @@ -94,7 +94,7 @@ class BranchRegReg64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Branch to a target computed with a register @@ -110,7 +110,7 @@ class BranchReg64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Ret instruction @@ -123,7 +123,7 @@ class BranchRet64 : public BranchReg64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // RetAA/RetAB instruction @@ -136,7 +136,7 @@ class BranchRetA64 : public BranchRegReg64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Eret instruction @@ -148,7 +148,7 @@ class BranchEret64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // EretA/B instruction @@ -163,7 +163,7 @@ class BranchEretA64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Branch to a target computed with an immediate and a register class BranchImmReg64 : public ArmStaticInst @@ -185,7 +185,7 @@ class BranchImmReg64 : public ArmStaticInst using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // Branch to a target computed with two immediates @@ -211,7 +211,7 @@ class BranchImmImmReg64 : public ArmStaticInst using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/insts/data64.cc b/src/arch/arm/insts/data64.cc index fb8fb74cb..3c6b4fb98 100644 --- a/src/arch/arm/insts/data64.cc +++ b/src/arch/arm/insts/data64.cc @@ -41,7 +41,8 @@ namespace ArmISA { std::string -DataXImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataXImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, @@ -50,7 +51,8 @@ DataXImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataXImmOnlyOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -60,7 +62,8 @@ DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataXSRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataXSRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, @@ -69,7 +72,8 @@ DataXSRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataXERegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataXERegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, @@ -78,7 +82,8 @@ DataXERegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataX1RegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -89,7 +94,8 @@ DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataX1RegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -101,7 +107,8 @@ DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataX1Reg2ImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -113,7 +120,8 @@ DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataX2RegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -126,7 +134,8 @@ DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataX2RegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -140,7 +149,8 @@ DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataX3RegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -156,7 +166,7 @@ DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string DataXCondCompImmOp::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -169,7 +179,7 @@ DataXCondCompImmOp::generateDisassembly( std::string DataXCondCompRegOp::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -184,7 +194,7 @@ DataXCondCompRegOp::generateDisassembly( std::string DataXCondSelOp::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/data64.hh b/src/arch/arm/insts/data64.hh index dfd91f72f..352a7b198 100644 --- a/src/arch/arm/insts/data64.hh +++ b/src/arch/arm/insts/data64.hh @@ -57,7 +57,7 @@ class DataXImmOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataXImmOnlyOp : public ArmStaticInst @@ -73,7 +73,7 @@ class DataXImmOnlyOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataXSRegOp : public ArmStaticInst @@ -92,7 +92,7 @@ class DataXSRegOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataXERegOp : public ArmStaticInst @@ -111,7 +111,7 @@ class DataXERegOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataX1RegOp : public ArmStaticInst @@ -125,7 +125,7 @@ class DataX1RegOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataX1RegImmOp : public ArmStaticInst @@ -141,7 +141,7 @@ class DataX1RegImmOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataX1Reg2ImmOp : public ArmStaticInst @@ -158,7 +158,7 @@ class DataX1Reg2ImmOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataX2RegOp : public ArmStaticInst @@ -173,7 +173,7 @@ class DataX2RegOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataX2RegImmOp : public ArmStaticInst @@ -190,7 +190,7 @@ class DataX2RegImmOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataX3RegOp : public ArmStaticInst @@ -206,7 +206,7 @@ class DataX3RegOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataXCondCompImmOp : public ArmStaticInst @@ -225,7 +225,7 @@ class DataXCondCompImmOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataXCondCompRegOp : public ArmStaticInst @@ -243,7 +243,7 @@ class DataXCondCompRegOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataXCondSelOp : public ArmStaticInst @@ -260,7 +260,7 @@ class DataXCondSelOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 211a17626..187e6dba6 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -1506,7 +1506,8 @@ MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst, } std::string -MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroIntImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1519,7 +1520,8 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroIntImmXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroIntImmXOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1532,7 +1534,8 @@ MicroIntImmXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroSetPCCPSR::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1541,7 +1544,8 @@ MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroIntRegXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroIntRegXOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1553,7 +1557,8 @@ MicroIntRegXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroIntMov::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1564,7 +1569,8 @@ MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroIntOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1577,7 +1583,8 @@ MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroMemOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -1594,7 +1601,8 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MicroMemPairOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MicroMemPairOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 94a3e0fd1..050e7229d 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -262,7 +262,7 @@ class MicroSetPCCPSR : public MicroOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -281,7 +281,7 @@ class MicroIntMov : public MicroOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -301,7 +301,7 @@ class MicroIntImmOp : public MicroOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MicroIntImmXOp : public MicroOpX @@ -318,7 +318,7 @@ class MicroIntImmXOp : public MicroOpX } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -337,7 +337,7 @@ class MicroIntOp : public MicroOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MicroIntRegXOp : public MicroOp @@ -357,7 +357,7 @@ class MicroIntRegXOp : public MicroOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -397,7 +397,7 @@ class MicroMemOp : public MicroIntImmOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MicroMemPairOp : public MicroOp @@ -418,7 +418,7 @@ class MicroMemPairOp : public MicroOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index c594ba5b3..e44fc9614 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -76,7 +76,7 @@ MemoryReg::printOffset(std::ostream &os) const } string -RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; switch (mode) { @@ -101,7 +101,7 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } string -SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; switch (mode) { diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index 55d29812a..c7bd0ee11 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -108,7 +108,7 @@ class RfeOp : public MightBeMicro } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // The address is a base register plus an immediate. @@ -149,7 +149,7 @@ class SrsOp : public MightBeMicro } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class Memory : public MightBeMicro @@ -372,7 +372,7 @@ class MemoryOffset : public Base {} std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; this->printInst(ss, Memory::AddrMd_Offset); @@ -422,7 +422,7 @@ class MemoryPreIndex : public Base {} std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; this->printInst(ss, Memory::AddrMd_PreIndex); @@ -472,7 +472,7 @@ class MemoryPostIndex : public Base {} std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; this->printInst(ss, Memory::AddrMd_PostIndex); diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc index 02489092f..0ddda956e 100644 --- a/src/arch/arm/insts/mem64.cc +++ b/src/arch/arm/insts/mem64.cc @@ -47,7 +47,7 @@ namespace ArmISA { std::string -SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SysDC64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -86,7 +86,8 @@ Memory64::setExcAcRel(bool exclusive, bool acrel) } std::string -MemoryImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryImm64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; startDisassembly(ss); @@ -97,7 +98,8 @@ MemoryImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryDImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryDImm64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -113,7 +115,8 @@ MemoryDImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryDImmEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryDImmEx64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -131,7 +134,8 @@ MemoryDImmEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryPreIndex64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryPreIndex64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; startDisassembly(ss); @@ -140,7 +144,8 @@ MemoryPreIndex64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryPostIndex64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryPostIndex64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; startDisassembly(ss); @@ -151,7 +156,8 @@ MemoryPostIndex64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryReg64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryReg64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; startDisassembly(ss); @@ -161,7 +167,8 @@ MemoryReg64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryRaw64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryRaw64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; startDisassembly(ss); @@ -170,7 +177,8 @@ MemoryRaw64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryEx64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -184,7 +192,8 @@ MemoryEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemoryLiteral64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemoryLiteral64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh index 78477cebf..eb9ca5450 100644 --- a/src/arch/arm/insts/mem64.hh +++ b/src/arch/arm/insts/mem64.hh @@ -61,7 +61,7 @@ class SysDC64 : public MiscRegOp64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MightBeMicro64 : public ArmStaticInst @@ -142,7 +142,7 @@ class MemoryImm64 : public Memory64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryDImm64 : public MemoryImm64 @@ -158,7 +158,7 @@ class MemoryDImm64 : public MemoryImm64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryDImmEx64 : public MemoryDImm64 @@ -174,7 +174,7 @@ class MemoryDImmEx64 : public MemoryDImm64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryPreIndex64 : public MemoryImm64 @@ -187,7 +187,7 @@ class MemoryPreIndex64 : public MemoryImm64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryPostIndex64 : public MemoryImm64 @@ -200,7 +200,7 @@ class MemoryPostIndex64 : public MemoryImm64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryReg64 : public Memory64 @@ -219,7 +219,7 @@ class MemoryReg64 : public Memory64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryRaw64 : public Memory64 @@ -231,7 +231,7 @@ class MemoryRaw64 : public Memory64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryEx64 : public Memory64 @@ -246,7 +246,7 @@ class MemoryEx64 : public Memory64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MemoryLiteral64 : public Memory64 @@ -260,7 +260,7 @@ class MemoryLiteral64 : public Memory64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 999edef78..f1012be5e 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -41,7 +41,7 @@ #include "cpu/reg_class.hh" std::string -MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -124,7 +124,7 @@ MsrBase::printMsrBase(std::ostream &os) const } std::string -MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MsrImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMsrBase(ss); @@ -133,7 +133,7 @@ MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MsrRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMsrBase(ss); @@ -143,7 +143,7 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MrrcOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -156,7 +156,7 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +McrrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -169,7 +169,7 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +ImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -178,7 +178,7 @@ ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -188,7 +188,7 @@ RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -199,15 +199,17 @@ RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); printIntReg(ss, dest); return ss.str(); } + std::string -RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -221,7 +223,8 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegRegRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -236,7 +239,8 @@ RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -249,7 +253,8 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -261,7 +266,8 @@ RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MiscRegRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -272,7 +278,8 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegMiscRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -283,7 +290,8 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegImmImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -293,7 +301,8 @@ RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegImmImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -305,7 +314,8 @@ RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegImmRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -316,7 +326,8 @@ RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegImmRegShiftOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -328,7 +339,8 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +UnknownOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (inst %#08x)", "unknown", encoding()); } @@ -356,7 +368,8 @@ McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const } std::string -McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const +McrMrcMiscInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (pipe flush)", mnemonic); } @@ -382,8 +395,8 @@ McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const } std::string -McrMrcImplDefined::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +McrMrcImplDefined::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (implementation defined)", mnemonic); } diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 5d9c23170..9caae0ca4 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -51,7 +51,7 @@ class MrsOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MsrBase : public PredOp @@ -78,7 +78,7 @@ class MsrImmOp : public MsrBase {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MsrRegOp : public MsrBase @@ -92,7 +92,7 @@ class MsrRegOp : public MsrBase {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MrrcOp : public PredOp @@ -111,7 +111,7 @@ class MrrcOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class McrrOp : public PredOp @@ -130,7 +130,7 @@ class McrrOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class ImmOp : public PredOp @@ -144,7 +144,7 @@ class ImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegImmOp : public PredOp @@ -159,7 +159,7 @@ class RegImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegOp : public PredOp @@ -174,7 +174,7 @@ class RegRegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegOp : public PredOp @@ -188,7 +188,7 @@ class RegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegImmRegOp : public PredOp @@ -205,7 +205,7 @@ class RegImmRegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegRegImmOp : public PredOp @@ -224,7 +224,7 @@ class RegRegRegImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegRegRegOp : public PredOp @@ -243,7 +243,7 @@ class RegRegRegRegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegRegOp : public PredOp @@ -260,7 +260,7 @@ class RegRegRegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegImmOp : public PredOp @@ -278,7 +278,7 @@ class RegRegImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MiscRegRegImmOp : public PredOp @@ -296,7 +296,7 @@ class MiscRegRegImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegMiscRegImmOp : public PredOp @@ -314,7 +314,7 @@ class RegMiscRegImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegImmImmOp : public PredOp @@ -331,7 +331,7 @@ class RegImmImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegImmImmOp : public PredOp @@ -350,7 +350,7 @@ class RegRegImmImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegImmRegShiftOp : public PredOp @@ -371,7 +371,7 @@ class RegImmRegShiftOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class UnknownOp : public PredOp @@ -383,7 +383,7 @@ class UnknownOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -406,7 +406,7 @@ class McrMrcMiscInst : public ArmStaticInst Trace::InstRecord *traceData) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; @@ -424,7 +424,7 @@ class McrMrcImplDefined : public McrMrcMiscInst Trace::InstRecord *traceData) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 7342527ad..51e602863 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -39,7 +39,7 @@ #include "arch/arm/isa.hh" std::string -ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -48,7 +48,8 @@ ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegRegImmImmOp64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -61,7 +62,7 @@ RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string RegRegRegImmOp64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -75,7 +76,8 @@ RegRegRegImmOp64::generateDisassembly( } std::string -UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +UnknownOp64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (inst %#08x)", "unknown", encoding()); } @@ -374,7 +376,8 @@ MiscRegImmOp64::miscRegImm() const } std::string -MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MiscRegImmOp64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -386,7 +389,7 @@ MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string MiscRegRegImmOp64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -398,7 +401,7 @@ MiscRegRegImmOp64::generateDisassembly( std::string RegMiscRegImmOp64::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -432,8 +435,8 @@ MiscRegImplDefined64::execute(ExecContext *xc, } std::string -MiscRegImplDefined64::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +MiscRegImplDefined64::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (implementation defined)", fullMnemonic.c_str()); } diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index 0698b046e..30dd91603 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -51,7 +51,7 @@ class ImmOp64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegImmImmOp64 : public ArmStaticInst @@ -70,7 +70,7 @@ class RegRegImmImmOp64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegRegRegImmOp64 : public ArmStaticInst @@ -89,7 +89,7 @@ class RegRegRegImmOp64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class UnknownOp64 : public ArmStaticInst @@ -101,7 +101,7 @@ class UnknownOp64 : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -164,7 +164,7 @@ class MiscRegImmOp64 : public MiscRegOp64 RegVal miscRegImm() const; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MiscRegRegImmOp64 : public MiscRegOp64 @@ -182,7 +182,7 @@ class MiscRegRegImmOp64 : public MiscRegOp64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class RegMiscRegImmOp64 : public MiscRegOp64 @@ -200,7 +200,7 @@ class RegMiscRegImmOp64 : public MiscRegOp64 {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class MiscRegImplDefined64 : public MiscRegOp64 @@ -228,7 +228,7 @@ class MiscRegImplDefined64 : public MiscRegOp64 Trace::InstRecord *traceData) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; #endif diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc index 748b79a0a..9415c141a 100644 --- a/src/arch/arm/insts/pred_inst.cc +++ b/src/arch/arm/insts/pred_inst.cc @@ -43,7 +43,8 @@ namespace ArmISA { std::string -PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +PredIntOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; unsigned rotate = machInst.rotate * 2; @@ -60,7 +61,8 @@ PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +PredImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField, @@ -74,7 +76,8 @@ PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, @@ -83,7 +86,8 @@ DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, @@ -92,7 +96,8 @@ DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DataRegRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1, @@ -101,7 +106,8 @@ DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +PredMacroOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh index 5d7dc9767..8ba85c21c 100644 --- a/src/arch/arm/insts/pred_inst.hh +++ b/src/arch/arm/insts/pred_inst.hh @@ -250,7 +250,7 @@ class PredImmOp : public PredOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -271,7 +271,7 @@ class PredIntOp : public PredOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataImmOp : public PredOp @@ -290,7 +290,7 @@ class DataImmOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataRegOp : public PredOp @@ -309,7 +309,7 @@ class DataRegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class DataRegRegOp : public PredOp @@ -327,7 +327,7 @@ class DataRegRegOp : public PredOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -371,7 +371,7 @@ class PredMacroOp : public PredOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc index 9a1c9ac7a..5c2702b5b 100644 --- a/src/arch/arm/insts/pseudo.cc +++ b/src/arch/arm/insts/pseudo.cc @@ -97,7 +97,8 @@ DecoderFaultInst::faultName() const } std::string -DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const +DecoderFaultInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("gem5fault %s", faultName()); } @@ -131,7 +132,8 @@ FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const } std::string -FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FailUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); @@ -172,7 +174,8 @@ WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const } std::string -WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const +WarnUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh index defdf89c1..76dca20b0 100644 --- a/src/arch/arm/insts/pseudo.hh +++ b/src/arch/arm/insts/pseudo.hh @@ -57,7 +57,7 @@ class DecoderFaultInst : public ArmStaticInst Trace::InstRecord *traceData) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -83,7 +83,7 @@ class FailUnimplemented : public ArmStaticInst Trace::InstRecord *traceData) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -113,7 +113,7 @@ class WarnUnimplemented : public ArmStaticInst Trace::InstRecord *traceData) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 020539d88..b84aa810b 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -391,7 +391,7 @@ ArmStaticInst::printMnemonic(std::ostream &os, void ArmStaticInst::printTarget(std::ostream &os, Addr target, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { Addr symbolAddr; std::string symbol; @@ -472,7 +472,7 @@ ArmStaticInst::printCondition(std::ostream &os, void ArmStaticInst::printMemSymbol(std::ostream &os, - const SymbolTable *symtab, + const Loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const @@ -617,7 +617,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm, std::string ArmStaticInst::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 31a7d35d8..ce6569a7a 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -169,10 +169,10 @@ class ArmStaticInst : public StaticInst bool withCond64 = false, ConditionCode cond64 = COND_UC) const; void printTarget(std::ostream &os, Addr target, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; void printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const; - void printMemSymbol(std::ostream &os, const SymbolTable *symtab, + void printMemSymbol(std::ostream &os, const Loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const; void printShiftOperand(std::ostream &os, IntRegIndex rm, @@ -196,7 +196,7 @@ class ArmStaticInst : public StaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; static inline uint32_t cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc index ec0132fcb..0b8258ccf 100644 --- a/src/arch/arm/insts/sve.cc +++ b/src/arch/arm/insts/sve.cc @@ -56,7 +56,7 @@ svePredTypeToStr(SvePredType pt) std::string SvePredCountPredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -69,7 +69,8 @@ SvePredCountPredOp::generateDisassembly(Addr pc, } std::string -SvePredCountOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SvePredCountOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -89,7 +90,8 @@ SvePredCountOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveIndexIIOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveIndexIIOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -99,7 +101,8 @@ SveIndexIIOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveIndexIROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveIndexIROp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -110,7 +113,8 @@ SveIndexIROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveIndexRIOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveIndexRIOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -122,7 +126,8 @@ SveIndexRIOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveIndexRROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveIndexRROp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -135,7 +140,8 @@ SveIndexRROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveWhileOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveWhileOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -153,7 +159,8 @@ SveWhileOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveCompTermOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveCompTermOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -164,7 +171,8 @@ SveCompTermOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveUnaryPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveUnaryPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -177,7 +185,8 @@ SveUnaryPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveUnaryUnpredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveUnaryUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -188,8 +197,8 @@ SveUnaryUnpredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveUnaryWideImmUnpredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveUnaryWideImmUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -200,8 +209,8 @@ SveUnaryWideImmUnpredOp::generateDisassembly(Addr pc, } std::string -SveUnaryWideImmPredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveUnaryWideImmPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -215,8 +224,8 @@ SveUnaryWideImmPredOp::generateDisassembly(Addr pc, } std::string -SveBinImmUnpredConstrOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinImmUnpredConstrOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -229,7 +238,8 @@ SveBinImmUnpredConstrOp::generateDisassembly(Addr pc, } std::string -SveBinImmPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveBinImmPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -244,8 +254,8 @@ SveBinImmPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveBinWideImmUnpredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinWideImmUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -258,8 +268,8 @@ SveBinWideImmUnpredOp::generateDisassembly(Addr pc, } std::string -SveBinDestrPredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinDestrPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -274,8 +284,8 @@ SveBinDestrPredOp::generateDisassembly(Addr pc, } std::string -SveBinConstrPredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinConstrPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -293,7 +303,8 @@ SveBinConstrPredOp::generateDisassembly(Addr pc, } std::string -SveBinUnpredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveBinUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -306,8 +317,8 @@ SveBinUnpredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveBinIdxUnpredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinIdxUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -323,7 +334,8 @@ SveBinIdxUnpredOp::generateDisassembly(Addr pc, } std::string -SvePredLogicalOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SvePredLogicalOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -342,7 +354,8 @@ SvePredLogicalOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SvePredBinPermOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SvePredBinPermOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -355,7 +368,7 @@ SvePredBinPermOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveCmpOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveCmpOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -370,7 +383,8 @@ SveCmpOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveCmpImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveCmpImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -385,7 +399,8 @@ SveCmpImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveTerPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveTerPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -400,8 +415,8 @@ SveTerPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveTerImmUnpredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveTerImmUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -416,8 +431,8 @@ SveTerImmUnpredOp::generateDisassembly(Addr pc, } std::string -SveReducOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveReducOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -430,8 +445,8 @@ SveReducOp::generateDisassembly(Addr pc, } std::string -SveOrdReducOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveOrdReducOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -446,8 +461,8 @@ SveOrdReducOp::generateDisassembly(Addr pc, } std::string -SvePtrueOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePtrueOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -460,8 +475,8 @@ SvePtrueOp::generateDisassembly(Addr pc, } std::string -SveIntCmpOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveIntCmpOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -480,8 +495,8 @@ SveIntCmpOp::generateDisassembly(Addr pc, } std::string -SveIntCmpImmOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveIntCmpImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -496,7 +511,7 @@ SveIntCmpImmOp::generateDisassembly(Addr pc, } std::string -SveAdrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveAdrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -520,8 +535,8 @@ SveAdrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveElemCountOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveElemCountOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { static const char suffix[9] = {'\0', 'b', 'h', '\0', 'w', '\0', '\0', '\0', 'd'}; @@ -548,8 +563,8 @@ SveElemCountOp::generateDisassembly(Addr pc, } std::string -SvePartBrkOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePartBrkOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -562,8 +577,8 @@ SvePartBrkOp::generateDisassembly(Addr pc, } std::string -SvePartBrkPropOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePartBrkPropOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -578,8 +593,8 @@ SvePartBrkPropOp::generateDisassembly(Addr pc, } std::string -SveSelectOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveSelectOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -604,8 +619,8 @@ SveSelectOp::generateDisassembly(Addr pc, } std::string -SveUnaryPredPredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveUnaryPredPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -618,8 +633,7 @@ SveUnaryPredPredOp::generateDisassembly(Addr pc, } std::string -SveTblOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveTblOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -632,8 +646,8 @@ SveTblOp::generateDisassembly(Addr pc, } std::string -SveUnpackOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveUnpackOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -644,8 +658,8 @@ SveUnpackOp::generateDisassembly(Addr pc, } std::string -SvePredTestOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePredTestOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -656,8 +670,8 @@ SvePredTestOp::generateDisassembly(Addr pc, } std::string -SvePredUnaryWImplicitSrcOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePredUnaryWImplicitSrcOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -666,8 +680,8 @@ SvePredUnaryWImplicitSrcOp::generateDisassembly(Addr pc, } std::string -SvePredUnaryWImplicitSrcPredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePredUnaryWImplicitSrcPredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -679,8 +693,8 @@ SvePredUnaryWImplicitSrcPredOp::generateDisassembly(Addr pc, } std::string -SvePredUnaryWImplicitDstOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SvePredUnaryWImplicitDstOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -689,8 +703,8 @@ SvePredUnaryWImplicitDstOp::generateDisassembly(Addr pc, } std::string -SveWImplicitSrcDstOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveWImplicitSrcDstOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -698,8 +712,8 @@ SveWImplicitSrcDstOp::generateDisassembly(Addr pc, } std::string -SveBinImmUnpredDestrOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinImmUnpredDestrOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -714,8 +728,8 @@ SveBinImmUnpredDestrOp::generateDisassembly(Addr pc, } std::string -SveBinImmIdxUnpredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveBinImmIdxUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -729,8 +743,8 @@ SveBinImmIdxUnpredOp::generateDisassembly(Addr pc, } std::string -SveUnarySca2VecUnpredOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveUnarySca2VecUnpredOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -745,8 +759,8 @@ SveUnarySca2VecUnpredOp::generateDisassembly(Addr pc, } std::string -SveDotProdIdxOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveDotProdIdxOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -762,8 +776,8 @@ SveDotProdIdxOp::generateDisassembly(Addr pc, } std::string -SveDotProdOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveDotProdOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -776,8 +790,8 @@ SveDotProdOp::generateDisassembly(Addr pc, } std::string -SveComplexOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveComplexOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -796,8 +810,8 @@ SveComplexOp::generateDisassembly(Addr pc, } std::string -SveComplexIdxOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveComplexIdxOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh index 9ee59f8c1..36f2ad11f 100644 --- a/src/arch/arm/insts/sve.hh +++ b/src/arch/arm/insts/sve.hh @@ -65,7 +65,8 @@ class SveIndexIIOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), imm1(_imm1), imm2(_imm2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class SveIndexIROp : public ArmStaticInst { @@ -80,7 +81,8 @@ class SveIndexIROp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), imm1(_imm1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class SveIndexRIOp : public ArmStaticInst { @@ -95,7 +97,8 @@ class SveIndexRIOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm2(_imm2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class SveIndexRROp : public ArmStaticInst { @@ -110,7 +113,8 @@ class SveIndexRROp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; // Predicate count SVE instruction. @@ -128,7 +132,8 @@ class SvePredCountOp : public ArmStaticInst { dest(_dest), gp(_gp), srcIs32b(_srcIs32b), destIsVec(_destIsVec) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; // Predicate count SVE instruction (predicated). @@ -144,7 +149,8 @@ class SvePredCountPredOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// While predicate generation SVE instruction. @@ -159,7 +165,8 @@ class SveWhileOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Compare and terminate loop SVE instruction. @@ -172,7 +179,8 @@ class SveCompTermOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Unary, constructive, predicated (merging) SVE instruction. @@ -186,7 +194,8 @@ class SveUnaryPredOp : public ArmStaticInst { dest(_dest), op1(_op1), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Unary, constructive, unpredicated SVE instruction. @@ -200,7 +209,8 @@ class SveUnaryUnpredOp : public ArmStaticInst { dest(_dest), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Unary with wide immediate, constructive, unpredicated SVE instruction. @@ -216,7 +226,8 @@ class SveUnaryWideImmUnpredOp : public ArmStaticInst { dest(_dest), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Unary with wide immediate, constructive, predicated SVE instruction. @@ -235,7 +246,8 @@ class SveUnaryWideImmPredOp : public ArmStaticInst { dest(_dest), imm(_imm), gp(_gp), isMerging(_isMerging) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary with immediate, destructive, unpredicated SVE instruction. @@ -251,7 +263,8 @@ class SveBinImmUnpredConstrOp : public ArmStaticInst { dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary with immediate, destructive, predicated (merging) SVE instruction. @@ -266,7 +279,8 @@ class SveBinImmPredOp : public ArmStaticInst { dest(_dest), gp(_gp), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary with wide immediate, destructive, unpredicated SVE instruction. @@ -282,7 +296,8 @@ class SveBinWideImmUnpredOp : public ArmStaticInst { dest(_dest), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary, destructive, predicated (merging) SVE instruction. @@ -297,7 +312,8 @@ class SveBinDestrPredOp : public ArmStaticInst { dest(_dest), op2(_op2), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary, constructive, predicated SVE instruction. @@ -314,7 +330,8 @@ class SveBinConstrPredOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), gp(_gp), predType(_predType) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary, unpredicated SVE instruction with indexed operand @@ -328,7 +345,8 @@ class SveBinUnpredOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary, unpredicated SVE instruction @@ -344,7 +362,8 @@ class SveBinIdxUnpredOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), index(_index) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Predicate logical instruction. @@ -360,7 +379,8 @@ class SvePredLogicalOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), gp(_gp), isSel(_isSel) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Predicate binary permute instruction. @@ -375,7 +395,8 @@ class SvePredBinPermOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE compare instructions, predicated (zeroing). @@ -390,7 +411,8 @@ class SveCmpOp : public ArmStaticInst { dest(_dest), gp(_gp), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE compare-with-immediate instructions, predicated (zeroing). @@ -406,7 +428,8 @@ class SveCmpImmOp : public ArmStaticInst { dest(_dest), gp(_gp), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Ternary, destructive, predicated (merging) SVE instruction. @@ -421,7 +444,8 @@ class SveTerPredOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Ternary with immediate, destructive, unpredicated SVE instruction. @@ -437,7 +461,8 @@ class SveTerImmUnpredOp : public ArmStaticInst { dest(_dest), op2(_op2), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE reductions. @@ -451,7 +476,8 @@ class SveReducOp : public ArmStaticInst { dest(_dest), op1(_op1), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE ordered reductions. @@ -465,7 +491,8 @@ class SveOrdReducOp : public ArmStaticInst { dest(_dest), op1(_op1), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// PTRUE, PTRUES. @@ -480,7 +507,8 @@ class SvePtrueOp : public ArmStaticInst { dest(_dest), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Integer compare SVE instruction. @@ -497,7 +525,8 @@ class SveIntCmpOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Integer compare with immediate SVE instruction. @@ -514,7 +543,8 @@ class SveIntCmpImmOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm(_imm), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// ADR. @@ -539,7 +569,8 @@ class SveAdrOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), mult(_mult), offsetFormat(_offsetFormat) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Element count SVE instruction. @@ -559,7 +590,8 @@ class SveElemCountOp : public ArmStaticInst { dest(_dest), pattern(_pattern), imm(_imm), dstIsVec(_dstIsVec), dstIs32b(_dstIs32b) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Partition break SVE instruction. @@ -576,7 +608,8 @@ class SvePartBrkOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Partition break with propagation SVE instruction. @@ -593,7 +626,8 @@ class SvePartBrkPropOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Scalar element select SVE instruction. @@ -616,7 +650,8 @@ class SveSelectOp : public ArmStaticInst { dest(_dest), op1(_op1), gp(_gp), conditional(_conditional), scalar(_scalar), simdFp(_simdFp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE unary operation on predicate (predicated) @@ -632,7 +667,8 @@ class SveUnaryPredPredOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE table lookup/permute using vector of element indices (TBL) @@ -647,7 +683,8 @@ class SveTblOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE unpack and widen predicate @@ -661,7 +698,8 @@ class SveUnpackOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE predicate test @@ -675,7 +713,8 @@ class SvePredTestOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), op1(_op1), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE unary predicate instructions with implicit source operand @@ -688,7 +727,8 @@ class SvePredUnaryWImplicitSrcOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE unary predicate instructions, predicated, with implicit source operand @@ -703,7 +743,8 @@ class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), gp(_gp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE unary predicate instructions with implicit destination operand @@ -716,7 +757,8 @@ class SvePredUnaryWImplicitDstOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE unary predicate instructions with implicit destination operand @@ -726,7 +768,8 @@ class SveWImplicitSrcDstOp : public ArmStaticInst { OpClass __opClass) : ArmStaticInst(mnem, _machInst, __opClass) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE vector - immediate binary operation @@ -742,7 +785,8 @@ class SveBinImmUnpredDestrOp : public ArmStaticInst { ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Binary with immediate index, destructive, unpredicated SVE instruction. @@ -758,7 +802,8 @@ class SveBinImmIdxUnpredOp : public ArmStaticInst { dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// Unary unpredicated scalar to vector instruction @@ -774,7 +819,8 @@ class SveUnarySca2VecUnpredOp : public ArmStaticInst { dest(_dest), op1(_op1), simdFp(_simdFp) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE dot product instruction (indexed) @@ -792,7 +838,8 @@ class SveDotProdIdxOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE dot product instruction (vectors) @@ -809,7 +856,8 @@ class SveDotProdOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE Complex Instructions (vectors) @@ -826,7 +874,8 @@ class SveComplexOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), gp(_gp), rot(_rot) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /// SVE Complex Instructions (indexed) @@ -843,7 +892,8 @@ class SveComplexIdxOp : public ArmStaticInst { dest(_dest), op1(_op1), op2(_op2), rot(_rot), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh index eb1e33010..ed937a230 100644 --- a/src/arch/arm/insts/sve_macromem.hh +++ b/src/arch/arm/insts/sve_macromem.hh @@ -93,7 +93,7 @@ class SveLdStructSS : public PredMacroOp } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -165,7 +165,7 @@ class SveStStructSS : public PredMacroOp } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -237,7 +237,7 @@ class SveLdStructSI : public PredMacroOp } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -310,7 +310,7 @@ class SveStStructSI : public PredMacroOp } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -409,7 +409,7 @@ class SveIndexedMemVI : public PredMacroOp } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { // TODO: add suffix to transfer and base registers std::stringstream ss; @@ -513,7 +513,7 @@ class SveIndexedMemSV : public PredMacroOp } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { // TODO: add suffix to transfer and base registers std::stringstream ss; diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc index 466e4b945..7bdbb7241 100644 --- a/src/arch/arm/insts/sve_mem.cc +++ b/src/arch/arm/insts/sve_mem.cc @@ -41,8 +41,8 @@ namespace ArmISA { std::string -SveMemVecFillSpill::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveMemVecFillSpill::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -57,8 +57,8 @@ SveMemVecFillSpill::generateDisassembly(Addr pc, } std::string -SveMemPredFillSpill::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +SveMemPredFillSpill::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -73,7 +73,8 @@ SveMemPredFillSpill::generateDisassembly(Addr pc, } std::string -SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveContigMemSS::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { // TODO: add suffix to transfer register and scaling factor (LSL #) std::stringstream ss; @@ -92,7 +93,8 @@ SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SveContigMemSI::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { // TODO: add suffix to transfer register std::stringstream ss; diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh index 48651136c..157bc17ef 100644 --- a/src/arch/arm/insts/sve_mem.hh +++ b/src/arch/arm/insts/sve_mem.hh @@ -66,7 +66,8 @@ class SveMemVecFillSpill : public ArmStaticInst baseIsSP = isSP(_base); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class SveMemPredFillSpill : public ArmStaticInst @@ -91,7 +92,8 @@ class SveMemPredFillSpill : public ArmStaticInst baseIsSP = isSP(_base); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class SveContigMemSS : public ArmStaticInst @@ -117,7 +119,8 @@ class SveContigMemSS : public ArmStaticInst baseIsSP = isSP(_base); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class SveContigMemSI : public ArmStaticInst @@ -143,7 +146,8 @@ class SveContigMemSI : public ArmStaticInst baseIsSP = isSP(_base); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; } // namespace ArmISA diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc index bafca4338..85ca1bcec 100644 --- a/src/arch/arm/insts/vfp.cc +++ b/src/arch/arm/insts/vfp.cc @@ -45,7 +45,7 @@ std::string FpCondCompRegOp::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -60,7 +60,7 @@ FpCondCompRegOp::generateDisassembly( std::string FpCondSelOp::generateDisassembly( - Addr pc, const SymbolTable *symtab) const + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -75,7 +75,8 @@ FpCondSelOp::generateDisassembly( } std::string -FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FpRegRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -86,7 +87,8 @@ FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FpRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -96,7 +98,8 @@ FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FpRegRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -108,7 +111,8 @@ FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FpRegRegRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -121,7 +125,8 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) +FpRegRegRegCondOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -136,7 +141,8 @@ FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) } std::string -FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FpRegRegRegRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); @@ -151,7 +157,8 @@ FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FpRegRegRegImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh index 5eb681f7d..b58f00255 100644 --- a/src/arch/arm/insts/vfp.hh +++ b/src/arch/arm/insts/vfp.hh @@ -892,7 +892,7 @@ class FpCondCompRegOp : public FpOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpCondSelOp : public FpOp @@ -909,7 +909,7 @@ class FpCondSelOp : public FpOp {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegRegOp : public FpOp @@ -927,7 +927,7 @@ class FpRegRegOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegImmOp : public FpOp @@ -945,7 +945,7 @@ class FpRegImmOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegRegImmOp : public FpOp @@ -964,7 +964,7 @@ class FpRegRegImmOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegRegRegOp : public FpOp @@ -983,7 +983,7 @@ class FpRegRegRegOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegRegRegCondOp : public FpOp @@ -1005,7 +1005,7 @@ class FpRegRegRegCondOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegRegRegRegOp : public FpOp @@ -1026,7 +1026,7 @@ class FpRegRegRegRegOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class FpRegRegRegImmOp : public FpOp @@ -1048,7 +1048,7 @@ class FpRegRegRegImmOp : public FpOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa index fc31b2de2..896b95c6e 100644 --- a/src/arch/arm/isa/templates/sve_mem.isa +++ b/src/arch/arm/isa/templates/sve_mem.isa @@ -431,7 +431,7 @@ def template SveIndexedMemVIMicroopDeclare {{ } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { // TODO: add suffix to transfer register std::stringstream ss; @@ -510,7 +510,7 @@ def template SveIndexedMemSVMicroopDeclare {{ } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { // TODO: add suffix to transfer and base registers std::stringstream ss; @@ -735,7 +735,7 @@ def template SveFirstFaultWritebackMicroopDeclare {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); @@ -790,7 +790,7 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); @@ -862,7 +862,7 @@ def template SveStructMemSIMicroopDeclare {{ } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -1125,7 +1125,7 @@ def template SveStructMemSSMicroopDeclare {{ } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -1190,7 +1190,7 @@ def template SveIntrlvMicroopDeclare {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); @@ -1227,7 +1227,7 @@ def template SveDeIntrlvMicroopDeclare {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; ccprintf(ss, "%s", macroOp->disassemble(pc, symtab)); diff --git a/src/arch/arm/linux/fs_workload.cc b/src/arch/arm/linux/fs_workload.cc index 65f067598..cc28193d9 100644 --- a/src/arch/arm/linux/fs_workload.cc +++ b/src/arch/arm/linux/fs_workload.cc @@ -77,7 +77,8 @@ FsLinux::initState() // it is helpful. if (params()->early_kernel_symbols) { kernelObj->loadGlobalSymbols(kernelSymtab, 0, 0, _loadAddrMask); - kernelObj->loadGlobalSymbols(debugSymbolTable, 0, 0, _loadAddrMask); + kernelObj->loadGlobalSymbols( + Loader::debugSymbolTable, 0, 0, _loadAddrMask); } // Setup boot data structure @@ -94,7 +95,7 @@ FsLinux::initState() inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename, params()->atags_addr + _loadAddrOffset); - DtbFile *dtb_file = new DtbFile(params()->dtb_filename); + auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename); if (!dtb_file->addBootCmdLine( commandLine.c_str(), commandLine.size())) { @@ -184,7 +185,7 @@ FsLinux::startup() FsWorkload::startup(); if (enableContextSwitchStatsDump) { - if (getArch() == ObjectFile::Arm64) + if (getArch() == Loader::Arm64) dumpStats = addKernelFuncEvent("__switch_to"); else dumpStats = addKernelFuncEvent("__switch_to"); @@ -237,7 +238,7 @@ FsLinux::startup() "__const_udelay", "__const_udelay", 1000, 107374); } - if (getArch() == ObjectFile::Arm64) { + if (getArch() == Loader::Arm64) { debugPrintk = addKernelFuncEvent< DebugPrintk>("dprintk"); } else { diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index 02c9f27e9..b5b6553d9 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -64,30 +64,30 @@ class ArmLinuxObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { auto arch = obj_file->getArch(); auto opsys = obj_file->getOpSys(); - if (arch != ObjectFile::Arm && arch != ObjectFile::Thumb && - arch != ObjectFile::Arm64) { + if (arch != ::Loader::Arm && arch != ::Loader::Thumb && + arch != ::Loader::Arm64) { return nullptr; } - if (opsys == ObjectFile::UnknownOpSys) { + if (opsys == ::Loader::UnknownOpSys) { warn("Unknown operating system; assuming Linux."); - opsys = ObjectFile::Linux; + opsys = ::Loader::Linux; } - if (opsys == ObjectFile::LinuxArmOABI) { + if (opsys == ::Loader::LinuxArmOABI) { fatal("gem5 does not support ARM OABI binaries. Please recompile " "with an EABI compiler."); } - if (opsys != ObjectFile::Linux) + if (opsys != ::Loader::Linux) return nullptr; - if (arch == ObjectFile::Arm64) + if (arch == ::Loader::Arm64) return new ArmLinuxProcess64(params, obj_file, arch); else return new ArmLinuxProcess32(params, obj_file, arch); @@ -850,12 +850,12 @@ static SyscallDescTable privSyscallDescs64 = { }; ArmLinuxProcess32::ArmLinuxProcess32(ProcessParams * params, - ObjectFile *objFile, ObjectFile::Arch _arch) : + ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) : ArmProcess32(params, objFile, _arch) {} ArmLinuxProcess64::ArmLinuxProcess64(ProcessParams * params, - ObjectFile *objFile, ObjectFile::Arch _arch) : + ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) : ArmProcess64(params, objFile, _arch) {} diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh index 46801cb00..0662d9f60 100644 --- a/src/arch/arm/linux/process.hh +++ b/src/arch/arm/linux/process.hh @@ -77,8 +77,8 @@ struct Resultname, params->pid, PageBytes), objFile), @@ -68,8 +68,8 @@ ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile, fatal_if(params->useArchPT, "Arch page tables not implemented."); } -ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, - ObjectFile::Arch _arch) +ArmProcess32::ArmProcess32(ProcessParams *params, + ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) : ArmProcess(params, objFile, _arch) { Addr brk_point = roundUp(image.maxAddr(), PageBytes); @@ -83,8 +83,9 @@ ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, mmap_end); } -ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile, - ObjectFile::Arch _arch) +ArmProcess64::ArmProcess64( + ProcessParams *params, ::Loader::ObjectFile *objFile, + ::Loader::Arch _arch) : ArmProcess(params, objFile, _arch) { Addr brk_point = roundUp(image.maxAddr(), PageBytes); @@ -267,10 +268,10 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) //Setup the auxilliary vectors. These will already have endian conversion. //Auxilliary vectors are loaded only for elf formatted executables. - ElfObject * elfObject = dynamic_cast(objFile); + auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile); if (elfObject) { - if (objFile->getOpSys() == ObjectFile::Linux) { + if (objFile->getOpSys() == ::Loader::Linux) { IntType features = armHwcap(); //Bits which describe the system hardware capabilities @@ -461,9 +462,9 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) } PCState pc; - pc.thumb(arch == ObjectFile::Thumb); + pc.thumb(arch == ::Loader::Thumb); pc.nextThumb(pc.thumb()); - pc.aarch64(arch == ObjectFile::Arm64); + pc.aarch64(arch == ::Loader::Arm64); pc.nextAArch64(pc.aarch64()); pc.set(getStartPC() & ~mask(1)); tc->pcState(pc); diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh index 3d0e34937..d06945462 100644 --- a/src/arch/arm/process.hh +++ b/src/arch/arm/process.hh @@ -50,14 +50,12 @@ #include "sim/process.hh" #include "sim/syscall_abi.hh" -class ObjectFile; - class ArmProcess : public Process { protected: - ObjectFile::Arch arch; - ArmProcess(ProcessParams * params, ObjectFile *objFile, - ObjectFile::Arch _arch); + ::Loader::Arch arch; + ArmProcess(ProcessParams * params, ::Loader::ObjectFile *objFile, + ::Loader::Arch _arch); template void argsInit(int pageSize, ArmISA::IntRegIndex spIndex); @@ -76,8 +74,8 @@ class ArmProcess : public Process class ArmProcess32 : public ArmProcess { protected: - ArmProcess32(ProcessParams * params, ObjectFile *objFile, - ObjectFile::Arch _arch); + ArmProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile, + ::Loader::Arch _arch); void initState() override; @@ -119,8 +117,8 @@ struct ArgumentgetVirtProxy(); - const SymbolTable *symtab = tc->getSystemPtr()->workload->symtab(tc); + const auto *symtab = tc->getSystemPtr()->workload->symtab(tc); Addr addr; if (!symtab->findAddress(name, addr)) diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc index dd3b9a557..8eb37b7b3 100644 --- a/src/arch/arm/system.cc +++ b/src/arch/arm/system.cc @@ -82,7 +82,7 @@ ArmSystem::ArmSystem(Params *p) workload->getEntry(), _resetAddr); } - bool wl_is_64 = (workload->getArch() == ObjectFile::Arm64); + bool wl_is_64 = (workload->getArch() == Loader::Arm64); if (wl_is_64 != _highestELIs64) { warn("Highest ARM exception-level set to AArch%d but the workload " "is for AArch%d. Assuming you wanted these to match.", diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa index 54647300b..0d514671a 100644 --- a/src/arch/mips/isa/base.isa +++ b/src/arch/mips/isa/base.isa @@ -54,7 +54,7 @@ output header {{ void printReg(std::ostream &os, RegId reg) const; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; public: void @@ -75,17 +75,19 @@ output header {{ //Ouputs to decoder.cc output decoder {{ - void MipsStaticInst::printReg(std::ostream &os, RegId reg) const + void + MipsStaticInst::printReg(std::ostream &os, RegId reg) const { if (reg.isIntReg()) { ccprintf(os, "r%d", reg.index()); - } - else { + } else { ccprintf(os, "f%d", reg.index()); } } - std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string + MipsStaticInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa index b42e39fc1..06662f092 100644 --- a/src/arch/mips/isa/formats/branch.isa +++ b/src/arch/mips/isa/formats/branch.isa @@ -52,7 +52,7 @@ output header {{ mutable Addr cachedPC; /// Cached symbol table pointer from last disassembly - mutable const SymbolTable *cachedSymtab; + mutable const Loader::SymbolTable *cachedSymtab; /// Constructor PCDependentDisassembly(const char *mnem, MachInst _machInst, @@ -63,7 +63,7 @@ output header {{ } const std::string & - disassemble(Addr pc, const SymbolTable *symtab) const; + disassemble(Addr pc, const Loader::SymbolTable *symtab) const; }; /** @@ -94,7 +94,7 @@ output header {{ using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -124,7 +124,7 @@ output header {{ using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; @@ -151,8 +151,8 @@ output decoder {{ } const std::string & - PCDependentDisassembly::disassemble(Addr pc, - const SymbolTable *symtab) const + PCDependentDisassembly::disassemble( + Addr pc, const Loader::SymbolTable *symtab) const { if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) @@ -170,7 +170,8 @@ output decoder {{ } std::string - Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + Branch::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -202,7 +203,7 @@ output decoder {{ } std::string - Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const + Jump::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index be7b18b2b..bb75ea838 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -33,146 +33,134 @@ //Outputs to decoder.hh output header {{ - - class CP0Control : public MipsStaticInst - { - protected: - - /// Constructor - CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - class CP0TLB : public MipsStaticInst - { - protected: - - /// Constructor - CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - - - class CP1Control : public MipsStaticInst - { - protected: - - /// Constructor - CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - + class CP0Control : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + class CP0TLB : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + + + class CP1Control : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; }}; // Basic instruction class execute method template. def template CP0Execute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - %(op_decl)s; - %(op_rd)s; - - if (isCoprocessorEnabled(xc, 0)) { - %(code)s; - - if(fault == NoFault) - { - %(op_wb)s; - } - } else { - fault = std::make_shared(0); - } - return fault; + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + + if (isCoprocessorEnabled(xc, 0)) { + %(code)s; + + if(fault == NoFault) + { + %(op_wb)s; + } + } else { + fault = std::make_shared(0); } + return fault; + } }}; def template CP1Execute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - %(op_decl)s; - %(op_rd)s; - - if (isCoprocessorEnabled(xc, 1)) { - %(code)s; - } else { - fault = std::make_shared(1); - } + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + + if (isCoprocessorEnabled(xc, 1)) { + %(code)s; + } else { + fault = std::make_shared(1); + } - if(fault == NoFault) - { - %(op_wb)s; - } - return fault; + if(fault == NoFault) + { + %(op_wb)s; } + return fault; + } }}; // Basic instruction class execute method template. def template ControlTLBExecute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - %(op_decl)s; - %(op_rd)s; - - if (FullSystem) { - if (isCoprocessor0Enabled(xc)) { - if(isMMUTLB(xc)){ - %(code)s; - } else { - fault = std::make_shared(); - } + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + + if (FullSystem) { + if (isCoprocessor0Enabled(xc)) { + if(isMMUTLB(xc)){ + %(code)s; } else { - fault = std::make_shared(0); + fault = std::make_shared(); } - } else { // Syscall Emulation Mode - No TLB Instructions - fault = std::make_shared(); + } else { + fault = std::make_shared(0); } + } else { // Syscall Emulation Mode - No TLB Instructions + fault = std::make_shared(); + } - if (fault == NoFault) { - %(op_wb)s; - } - return fault; + if (fault == NoFault) { + %(op_wb)s; } + return fault; + } }}; //Outputs to decoder.cc output decoder {{ - std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); - return ss.str(); - } - std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); - return ss.str(); - } - std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS); - return ss.str(); - } - + std::string + CP0Control::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; + ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); + return ss.str(); + } + std::string + CP0TLB::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; + ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL); + return ss.str(); + } + std::string + CP1Control::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; + ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS); + return ss.str(); + } }}; output header {{ diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 901e67316..5d8f10755 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -32,187 +32,182 @@ // output header {{ - /** - * Base class for FP operations. - */ - class FPOp : public MipsStaticInst - { - protected: - - /// Constructor - FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - //needs function to check for fpEnable or not - }; - - class FPCompareOp : public FPOp - { - protected: - FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; + /** + * Base class for FP operations. + */ + class FPOp : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; + + //needs function to check for fpEnable or not + }; + + class FPCompareOp : public FPOp + { + protected: + using FPOp::FPOp; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; }}; output decoder {{ - std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; + std::string + FPCompareOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; - ccprintf(ss, "%-10s ", mnemonic); + ccprintf(ss, "%-10s ", mnemonic); - ccprintf(ss,"%d",CC); + ccprintf(ss,"%d",CC); - if(_numSrcRegs > 0) { - ss << ", "; - printReg(ss, _srcRegIdx[0]); - } - - if(_numSrcRegs > 1) { - ss << ", "; - printReg(ss, _srcRegIdx[1]); - } + if (_numSrcRegs > 0) { + ss << ", "; + printReg(ss, _srcRegIdx[0]); + } - return ss.str(); + if (_numSrcRegs > 1) { + ss << ", "; + printReg(ss, _srcRegIdx[1]); } + + return ss.str(); + } }}; output header {{ - void fpResetCauseBits(ExecContext *cpu); - + void fpResetCauseBits(ExecContext *cpu); }}; output exec {{ - inline Fault checkFpEnableFault(ExecContext *xc) - { - //@TODO: Implement correct CP0 checks to see if the CP1 - // unit is enable or not - if (!isCoprocessorEnabled(xc, 1)) - return std::make_shared(1); - - return NoFault; - } - - //If any operand is Nan return the appropriate QNaN - template - bool - fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type, - Trace::InstRecord *traceData) - { - uint64_t mips_nan = 0; - assert(sizeof(T) == 4); - - for (int i = 0; i < inst->numSrcRegs(); i++) { - uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); - - if (isNan(&src_bits, 32) ) { - mips_nan = MIPS32_QNAN; - xc->setFloatRegOperandBits(inst, 0, mips_nan); - if (traceData) { traceData->setData(mips_nan); } - return true; - } + inline Fault + checkFpEnableFault(ExecContext *xc) + { + //@TODO: Implement correct CP0 checks to see if the CP1 + // unit is enable or not + if (!isCoprocessorEnabled(xc, 1)) + return std::make_shared(1); + + return NoFault; + } + + //If any operand is Nan return the appropriate QNaN + template + bool + fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type, + Trace::InstRecord *traceData) + { + uint64_t mips_nan = 0; + assert(sizeof(T) == 4); + + for (int i = 0; i < inst->numSrcRegs(); i++) { + uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); + + if (isNan(&src_bits, 32) ) { + mips_nan = MIPS32_QNAN; + xc->setFloatRegOperandBits(inst, 0, mips_nan); + if (traceData) { traceData->setData(mips_nan); } + return true; } - return false; } + return false; + } - template - bool - fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val, - Trace::InstRecord *traceData) - { - uint64_t mips_nan = 0; - T src_op = dest_val; - assert(sizeof(T) == 4); + template + bool + fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val, + Trace::InstRecord *traceData) + { + uint64_t mips_nan = 0; + T src_op = dest_val; + assert(sizeof(T) == 4); - if (isNan(&src_op, 32)) { - mips_nan = MIPS32_QNAN; + if (isNan(&src_op, 32)) { + mips_nan = MIPS32_QNAN; - //Set value to QNAN - cpu->setFloatRegOperandBits(inst, 0, mips_nan); + //Set value to QNAN + cpu->setFloatRegOperandBits(inst, 0, mips_nan); - //Read FCSR from FloatRegFile - uint32_t fcsr_bits = - cpu->tcBase()->readFloatReg(FLOATREG_FCSR); - - uint32_t new_fcsr = genInvalidVector(fcsr_bits); + //Read FCSR from FloatRegFile + uint32_t fcsr_bits = + cpu->tcBase()->readFloatReg(FLOATREG_FCSR); - //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr); + uint32_t new_fcsr = genInvalidVector(fcsr_bits); - if (traceData) { traceData->setData(mips_nan); } - return true; - } + //Write FCSR from FloatRegFile + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr); - return false; + if (traceData) { traceData->setData(mips_nan); } + return true; } - void - fpResetCauseBits(ExecContext *cpu) - { - //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR); + return false; + } - // TODO: Use utility function here - fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); + void + fpResetCauseBits(ExecContext *cpu) + { + //Read FCSR from FloatRegFile + uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR); - //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr); - } + // TODO: Use utility function here + fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); + + //Write FCSR from FloatRegFile + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr); + } }}; def template FloatingPointExecute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(fp_enable_check)s; - - - //When is the right time to reset cause bits? - //start of every instruction or every cycle? - if (FullSystem) - fpResetCauseBits(xc); - %(op_decl)s; - %(op_rd)s; - - //Check if any FP operand is a NaN value - if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { - %(code)s; - - //Change this code for Full-System/Sycall Emulation - //separation - //---- - //Should Full System-Mode throw a fault here? - //---- - //Check for IEEE 754 FP Exceptions - //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); - bool invalid_op = false; - if (FullSystem) { - invalid_op = - fpInvalidOp((FPOp*)this, xc, Fd, traceData); - } - if (!invalid_op && fault == NoFault) { - %(op_wb)s; - } - } - - return fault; + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(fp_enable_check)s; + + //When is the right time to reset cause bits? + //start of every instruction or every cycle? + if (FullSystem) + fpResetCauseBits(xc); + %(op_decl)s; + %(op_rd)s; + + //Check if any FP operand is a NaN value + if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { + %(code)s; + + //Change this code for Full-System/Sycall Emulation + //separation + //---- + //Should Full System-Mode throw a fault here? + //---- + //Check for IEEE 754 FP Exceptions + //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); + bool invalid_op = false; + if (FullSystem) { + invalid_op = + fpInvalidOp((FPOp*)this, xc, Fd, traceData); + } + if (!invalid_op && fault == NoFault) { + %(op_wb)s; + } } + + return fault; + } }}; // Primary format for float point operate instructions: def format FloatOp(code, *flags) {{ - iop = InstObjParams(name, Name, 'FPOp', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = FloatingPointExecute.subst(iop) + iop = InstObjParams(name, Name, 'FPOp', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = FloatingPointExecute.subst(iop) }}; def format FloatCompareOp(cond_code, *flags) {{ @@ -306,20 +301,20 @@ def format FloatConvertOp(code, *flags) {{ }}; def format FloatAccOp(code, *flags) {{ - iop = InstObjParams(name, Name, 'FPOp', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + iop = InstObjParams(name, Name, 'FPOp', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; // Primary format for float64 operate instructions: def format Float64Op(code, *flags) {{ - iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa index 4bf9e3c22..c48ad1169 100644 --- a/src/arch/mips/isa/formats/int.isa +++ b/src/arch/mips/isa/formats/int.isa @@ -33,298 +33,277 @@ output header {{ #include using namespace std; - /** - * Base class for integer operations. - */ - class IntOp : public MipsStaticInst + /** + * Base class for integer operations. + */ + class IntOp : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + + + class HiLoOp: public IntOp + { + protected: + using IntOp::IntOp; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + + class HiLoRsSelOp: public HiLoOp + { + protected: + using HiLoOp::HiLoOp; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + + class HiLoRdSelOp: public HiLoOp + { + protected: + using HiLoOp::HiLoOp; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + + class HiLoRdSelValOp: public HiLoOp + { + protected: + using HiLoOp::HiLoOp; + + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + + class IntImmOp : public MipsStaticInst + { + protected: + int16_t imm; + int32_t sextImm; + uint32_t zextImm; + + IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass), imm(INTIMM), + sextImm(INTIMM), zextImm(0x0000FFFF & INTIMM) { - protected: - - /// Constructor - IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - - - class HiLoOp: public IntOp - { - protected: - - /// Constructor - HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - IntOp(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - - class HiLoRsSelOp: public HiLoOp - { - protected: - - /// Constructor - HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - HiLoOp(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - - class HiLoRdSelOp: public HiLoOp - { - protected: - - /// Constructor - HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - HiLoOp(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - - class HiLoRdSelValOp: public HiLoOp - { - protected: - - /// Constructor - HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - HiLoOp(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; + // If Bit 15 is 1 then sign extend. + int32_t temp = sextImm & 0x00008000; + if (temp > 0 && strcmp(mnemonic,"lui") != 0) { + sextImm |= 0xFFFF0000; + } + } - class IntImmOp : public MipsStaticInst - { - protected: - - int16_t imm; - int32_t sextImm; - uint32_t zextImm; - - /// Constructor - IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), - sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) - { - //If Bit 15 is 1 then Sign Extend - int32_t temp = sextImm & 0x00008000; - if (temp > 0 && strcmp(mnemonic,"lui") != 0) { - sextImm |= 0xFFFF0000; - } - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; }}; // HiLo instruction class execute method template. def template HiLoExecute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(code)s; - - if(fault == NoFault) - { - %(op_wb)s; - } - return fault; + Fault + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if(fault == NoFault) { + %(op_wb)s; } + return fault; + } }}; // HiLoRsSel instruction class execute method template. def template HiLoRsSelExecute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(op_decl)s; - - if( ACSRC > 0 && !isDspEnabled(xc) ) - { - fault = std::make_shared(); - } - else - { - %(op_rd)s; - %(code)s; - } - - if(fault == NoFault) - { - %(op_wb)s; - } - return fault; + Fault + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + + if (ACSRC > 0 && !isDspEnabled(xc)) { + fault = std::make_shared(); + } else { + %(op_rd)s; + %(code)s; + } + + if (fault == NoFault) { + %(op_wb)s; } + return fault; + } }}; // HiLoRdSel instruction class execute method template. def template HiLoRdSelExecute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(op_decl)s; - - if( ACDST > 0 && !isDspEnabled(xc) ) - { - fault = std::make_shared(); - } - else - { - %(op_rd)s; - %(code)s; - } - - if(fault == NoFault) - { - %(op_wb)s; - } - return fault; + Fault + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + + if (ACDST > 0 && !isDspEnabled(xc)) { + fault = std::make_shared(); + } else { + %(op_rd)s; + %(code)s; + } + + if (fault == NoFault) { + %(op_wb)s; } + return fault; + } }}; //Outputs to decoder.cc output decoder {{ - std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; + std::string + IntOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // just print the first dest... if there's a second one, + // it's generally implicit + if (_numDestRegs > 0) { + printReg(ss, _destRegIdx[0]); + ss << ", "; + } - ccprintf(ss, "%-10s ", mnemonic); + // just print the first two source regs... if there's + // a third one, it's a read-modify-write dest (Rc), + // e.g. for CMOVxx + if (_numSrcRegs > 0) { + printReg(ss, _srcRegIdx[0]); + } - // just print the first dest... if there's a second one, - // it's generally implicit - if (_numDestRegs > 0) { - printReg(ss, _destRegIdx[0]); - ss << ", "; - } + if (_numSrcRegs > 1) { + ss << ", "; + printReg(ss, _srcRegIdx[1]); + } - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - } + return ss.str(); + } - if (_numSrcRegs > 1) { - ss << ", "; - printReg(ss, _srcRegIdx[1]); - } + std::string + HiLoOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); - return ss.str(); + // Destination Registers are implicit for HI/LO ops + if (_numSrcRegs > 0) { + printReg(ss, _srcRegIdx[0]); } - std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; + if (_numSrcRegs > 1) { + ss << ", "; + printReg(ss, _srcRegIdx[1]); + } - ccprintf(ss, "%-10s ", mnemonic); + return ss.str(); + } - //Destination Registers are implicit for HI/LO ops - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - } + std::string + HiLoRsSelOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; - if (_numSrcRegs > 1) { - ss << ", "; - printReg(ss, _srcRegIdx[1]); - } + ccprintf(ss, "%-10s ", mnemonic); - return ss.str(); + if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { + printReg(ss, _destRegIdx[0]); + } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { + printReg(ss, _srcRegIdx[0]); } - std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; + return ss.str(); + } - ccprintf(ss, "%-10s ", mnemonic); + std::string + HiLoRdSelOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; - if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { - printReg(ss, _destRegIdx[0]); - } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { - printReg(ss, _srcRegIdx[0]); - } + ccprintf(ss, "%-10s ", mnemonic); - return ss.str(); + if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { + printReg(ss, _destRegIdx[0]); + } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { + printReg(ss, _srcRegIdx[0]); } - std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; + return ss.str(); + } - ccprintf(ss, "%-10s ", mnemonic); + std::string + HiLoRdSelValOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; - if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { - printReg(ss, _destRegIdx[0]); - } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { - printReg(ss, _srcRegIdx[0]); - } + ccprintf(ss, "%-10s ", mnemonic); - return ss.str(); + if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { + printReg(ss, _destRegIdx[0]); + } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { + printReg(ss, _srcRegIdx[0]); } - std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; + return ss.str(); + } - ccprintf(ss, "%-10s ", mnemonic); + std::string + IntImmOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + std::stringstream ss; - if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { - printReg(ss, _destRegIdx[0]); - } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { - printReg(ss, _srcRegIdx[0]); - } + ccprintf(ss, "%-10s ", mnemonic); - return ss.str(); + if (_numDestRegs > 0) { + printReg(ss, _destRegIdx[0]); } - std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - if (_numDestRegs > 0) { - printReg(ss, _destRegIdx[0]); - } + ss << ", "; + if (_numSrcRegs > 0) { + printReg(ss, _srcRegIdx[0]); ss << ", "; + } - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - ss << ", "; - } - - if(strcmp(mnemonic,"lui") == 0) - ccprintf(ss, "0x%x ", sextImm); - else - ss << (int) sextImm; + if(strcmp(mnemonic,"lui") == 0) + ccprintf(ss, "0x%x ", sextImm); + else + ss << (int) sextImm; - return ss.str(); - } + return ss.str(); + } }}; diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 7d9310d77..4f6f2eea6 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -44,7 +44,6 @@ output header {{ /// Displacement for EA calculation (signed). int32_t disp; - /// Constructor Memory(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass), disp(sext<16>(OFFSET)) @@ -52,7 +51,7 @@ output header {{ } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -62,28 +61,26 @@ output header {{ class MemoryNoDisp : public Memory { protected: - /// Constructor - MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : Memory(mnem, _machInst, __opClass) - { - } + using Memory::Memory; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; output decoder {{ std::string - Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const + Memory::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s %c%d, %d(r%d)", mnemonic, flags[IsFloating] ? 'f' : 'r', RT, disp, RS); } std::string - MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + MemoryNoDisp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, flags[IsFloating] ? 'f' : 'r', diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 1cd5447a7..fd09fadb3 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -32,40 +32,34 @@ // output header {{ - /** - * Base class for MIPS MT ASE operations. - */ - class MTOp : public MipsStaticInst - { - protected: - - /// Constructor - MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) - { - } + /** + * Base class for MIPS MT ASE operations. + */ + class MTOp : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; - bool user_mode; - }; + bool user_mode = false; + }; - class MTUserModeOp : public MTOp + class MTUserModeOp : public MTOp + { + protected: + MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MTOp(mnem, _machInst, __opClass) { - protected: - - /// Constructor - MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MTOp(mnem, _machInst, __opClass) - { - user_mode = true; - } - }; + user_mode = true; + } + }; }}; output decoder {{ - std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string + MTOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa index 24d6bb9fd..f361d49a7 100644 --- a/src/arch/mips/isa/formats/noop.isa +++ b/src/arch/mips/isa/formats/noop.isa @@ -52,15 +52,15 @@ output header {{ ~Nop() { } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; output decoder {{ - std::string Nop::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + Nop::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s %s", "nop", originalDisassembly); } diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa index ab9245f62..ed613be98 100644 --- a/src/arch/mips/isa/formats/tlbop.isa +++ b/src/arch/mips/isa/formats/tlbop.isa @@ -32,49 +32,47 @@ // output header {{ - /** - * Base class for integer operations. - */ - class TlbOp : public MipsStaticInst - { - protected: + /** + * Base class for integer operations. + */ + class TlbOp : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; - /// Constructor - TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; }}; output decoder {{ - std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } + std::string + TlbOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } }}; def template TlbOpExecute {{ - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - //Write the resulting state to the execution context - %(op_wb)s; + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + //Write the resulting state to the execution context + %(op_wb)s; - //Call into the trap handler with the appropriate fault - return No_Fault; - } + //Call into the trap handler with the appropriate fault + return No_Fault; + } }}; // Primary format for integer operate instructions: def format TlbOp(code, *opt_flags) {{ - orig_code = code - cblk = code - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = TlbOpExecute.subst(iop) + orig_code = code + cblk = code + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TlbOpExecute.subst(iop) }}; diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa index b813bbc62..669f131bd 100644 --- a/src/arch/mips/isa/formats/trap.isa +++ b/src/arch/mips/isa/formats/trap.isa @@ -32,82 +32,76 @@ // output header {{ - /** - * Base class for integer operations. - */ - class Trap : public MipsStaticInst - { - protected: + /** + * Base class for integer operations. + */ + class Trap : public MipsStaticInst + { + protected: + using MipsStaticInst::MipsStaticInst; - /// Constructor - Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; + class TrapImm : public MipsStaticInst + { + protected: + int16_t imm; - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; - class TrapImm : public MipsStaticInst - { - protected: - - int16_t imm; - - /// Constructor - TrapImm(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) - { - } - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; - }; + TrapImm(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass), imm(INTIMM) + {} + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; + }; }}; output decoder {{ - std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of trap instruction\n"; - } - std::string TrapImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of trap instruction\n"; - } + std::string + Trap::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + return "Disassembly of trap instruction\n"; + } + std::string + TrapImm::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + return "Disassembly of trap instruction\n"; + } }}; def template TrapExecute {{ - //Edit This Template When Traps Are Implemented - Fault %(class_name)s::execute( - ExecContext *xc, Trace::InstRecord *traceData) const - { - //Write the resulting state to the execution context - %(op_wb)s; + // Edit This Template When Traps Are Implemented + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + //Write the resulting state to the execution context + %(op_wb)s; - //Call into the trap handler with the appropriate fault - return No_Fault; - } + //Call into the trap handler with the appropriate fault + return No_Fault; + } }}; def format Trap(code, *flags) {{ + code ='bool cond;\n' + code + code += 'if (cond) {\n' + code += 'fault = std::make_shared();\n};' - code ='bool cond;\n' + code - code += 'if (cond) {\n' - code += 'fault = std::make_shared();\n};' - - iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; def format TrapImm(code, *flags) {{ - - code ='bool cond;\n' + code - code += 'if (cond) {\n' - code += 'fault = std::make_shared();\n};' - iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) + code ='bool cond;\n' + code + code += 'if (cond) {\n' + code += 'fault = std::make_shared();\n};' + iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa index 7e47b9148..cd0630d17 100644 --- a/src/arch/mips/isa/formats/unimp.isa +++ b/src/arch/mips/isa/formats/unimp.isa @@ -54,7 +54,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class CP0Unimplemented : public MipsStaticInst { @@ -71,7 +71,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class CP1Unimplemented : public MipsStaticInst { @@ -88,7 +88,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class CP2Unimplemented : public MipsStaticInst { @@ -105,7 +105,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -136,41 +136,41 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; output decoder {{ std::string - FailUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + FailUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } std::string - CP0Unimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + CP0Unimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } std::string - CP1Unimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + CP1Unimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } std::string - CP2Unimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + CP2Unimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } std::string - WarnUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + WarnUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa index cc1ac283f..c5ef70861 100644 --- a/src/arch/mips/isa/formats/unknown.isa +++ b/src/arch/mips/isa/formats/unknown.isa @@ -52,13 +52,14 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; output decoder {{ std::string - Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const + Unknown::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", "unknown", machInst, OPCODE, inst2string(machInst)); diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 7b759b604..b8b22674a 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -52,19 +52,19 @@ class MipsLinuxObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { - if (obj_file->getArch() != ObjectFile::Mips) + if (obj_file->getArch() != ::Loader::Mips) return nullptr; auto opsys = obj_file->getOpSys(); - if (opsys == ObjectFile::UnknownOpSys) { + if (opsys == ::Loader::UnknownOpSys) { warn("Unknown operating system; assuming Linux."); - opsys = ObjectFile::Linux; + opsys = ::Loader::Linux; } - if (opsys != ObjectFile::Linux) + if (opsys != ::Loader::Linux) return nullptr; return new MipsLinuxProcess(params, obj_file); @@ -475,7 +475,7 @@ SyscallDescTable MipsLinuxProcess::syscallDescs = { }; MipsLinuxProcess::MipsLinuxProcess(ProcessParams * params, - ObjectFile *objFile) : + ::Loader::ObjectFile *objFile) : MipsProcess(params, objFile) {} diff --git a/src/arch/mips/linux/process.hh b/src/arch/mips/linux/process.hh index dcf0c0878..ddf2a11c5 100644 --- a/src/arch/mips/linux/process.hh +++ b/src/arch/mips/linux/process.hh @@ -39,7 +39,7 @@ class MipsLinuxProcess : public MipsProcess { public: /// Constructor. - MipsLinuxProcess(ProcessParams * params, ObjectFile *objFile); + MipsLinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); /// The target system's hostname. static const char *hostname; diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index 3e7b378da..f6587ab8d 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -45,7 +45,7 @@ using namespace std; using namespace MipsISA; -MipsProcess::MipsProcess(ProcessParams *params, ObjectFile *objFile) +MipsProcess::MipsProcess(ProcessParams *params, ::Loader::ObjectFile *objFile) : Process(params, new EmulationPageTable(params->name, params->pid, PageBytes), objFile) @@ -88,7 +88,7 @@ MipsProcess::argsInit(int pageSize) std::vector> auxv; - ElfObject * elfObject = dynamic_cast(objFile); + auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile); if (elfObject) { // Set the system page size diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh index d7b233fe1..d236a8fff 100644 --- a/src/arch/mips/process.hh +++ b/src/arch/mips/process.hh @@ -36,12 +36,15 @@ #include "sim/process.hh" #include "sim/syscall_abi.hh" +namespace Loader +{ class ObjectFile; +} // namespace Loader class MipsProcess : public Process { protected: - MipsProcess(ProcessParams * params, ObjectFile *objFile); + MipsProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); void initState(); diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc index 4b75997bc..5fe0c4e8f 100644 --- a/src/arch/power/insts/branch.cc +++ b/src/arch/power/insts/branch.cc @@ -34,7 +34,8 @@ using namespace PowerISA; const std::string & -PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const +PCDependentDisassembly::disassemble( + Addr pc, const Loader::SymbolTable *symtab) const { if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) @@ -58,7 +59,8 @@ BranchPCRel::branchTarget(const PowerISA::PCState &pc) const } std::string -BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchPCRel::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -82,7 +84,8 @@ BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const } std::string -BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchNonPCRel::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -104,7 +107,8 @@ BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const } std::string -BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchPCRelCond::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -130,8 +134,8 @@ BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const } std::string -BranchNonPCRelCond::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +BranchNonPCRelCond::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -156,8 +160,8 @@ BranchRegCond::branchTarget(ThreadContext *tc) const } std::string -BranchRegCond::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +BranchRegCond::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh index fc1f327d8..435b4fdff 100644 --- a/src/arch/power/insts/branch.hh +++ b/src/arch/power/insts/branch.hh @@ -49,7 +49,7 @@ class PCDependentDisassembly : public PowerStaticInst /// Cached program counter from last disassembly mutable Addr cachedPC; /// Cached symbol table pointer from last disassembly - mutable const SymbolTable *cachedSymtab; + mutable const Loader::SymbolTable *cachedSymtab; /// Constructor PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, @@ -60,7 +60,7 @@ class PCDependentDisassembly : public PowerStaticInst } const std::string & - disassemble(Addr pc, const SymbolTable *symtab) const; + disassemble(Addr pc, const Loader::SymbolTable *symtab) const; }; /** @@ -90,7 +90,7 @@ class BranchPCRel : public PCDependentDisassembly using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -120,7 +120,7 @@ class BranchNonPCRel : public PCDependentDisassembly using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -199,7 +199,7 @@ class BranchPCRelCond : public BranchCond using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -229,7 +229,7 @@ class BranchNonPCRelCond : public BranchCond using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -251,7 +251,7 @@ class BranchRegCond : public BranchCond using StaticInst::branchTarget; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } // namespace PowerISA diff --git a/src/arch/power/insts/condition.cc b/src/arch/power/insts/condition.cc index 735249819..f08fcb477 100644 --- a/src/arch/power/insts/condition.cc +++ b/src/arch/power/insts/condition.cc @@ -31,7 +31,8 @@ using namespace PowerISA; std::string -CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +CondLogicOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; @@ -44,7 +45,8 @@ CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -CondMoveOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +CondMoveOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh index fdcc19711..a38f714dd 100644 --- a/src/arch/power/insts/condition.hh +++ b/src/arch/power/insts/condition.hh @@ -56,7 +56,7 @@ class CondLogicOp : public PowerStaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -78,7 +78,7 @@ class CondMoveOp : public PowerStaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } // namespace PowerISA diff --git a/src/arch/power/insts/floating.cc b/src/arch/power/insts/floating.cc index 19ec9819d..8bdaf1d21 100644 --- a/src/arch/power/insts/floating.cc +++ b/src/arch/power/insts/floating.cc @@ -31,7 +31,7 @@ using namespace PowerISA; std::string -FloatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +FloatOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh index 638193c7e..0acefdf0d 100644 --- a/src/arch/power/insts/floating.hh +++ b/src/arch/power/insts/floating.hh @@ -143,7 +143,7 @@ class FloatOp : public PowerStaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } // namespace PowerISA diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index 59c957c21..84362dea5 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -32,7 +32,7 @@ using namespace std; using namespace PowerISA; string -IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; bool printDest = true; @@ -79,7 +79,7 @@ IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const string -IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; @@ -115,7 +115,8 @@ IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const string -IntShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +IntShiftOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; @@ -142,7 +143,8 @@ IntShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const string -IntRotateOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +IntRotateOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh index 5521f73d2..1c9b1cc6c 100644 --- a/src/arch/power/insts/integer.hh +++ b/src/arch/power/insts/integer.hh @@ -90,7 +90,7 @@ class IntOp : public PowerStaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; @@ -113,7 +113,7 @@ class IntImmOp : public IntOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; @@ -134,7 +134,7 @@ class IntShiftOp : public IntOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; @@ -170,7 +170,7 @@ class IntRotateOp : public IntShiftOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } // namespace PowerISA diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc index 81c11eeb2..8566f04bb 100644 --- a/src/arch/power/insts/mem.cc +++ b/src/arch/power/insts/mem.cc @@ -33,13 +33,14 @@ using namespace PowerISA; std::string -MemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s", mnemonic); } std::string -MemDispOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemDispOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh index 3d3507f68..de9b46cdb 100644 --- a/src/arch/power/insts/mem.hh +++ b/src/arch/power/insts/mem.hh @@ -52,7 +52,7 @@ class MemOp : public PowerStaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; @@ -72,7 +72,7 @@ class MemDispOp : public MemOp } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } // namespace PowerISA diff --git a/src/arch/power/insts/misc.cc b/src/arch/power/insts/misc.cc index 6df3bb68b..5d12eb5d0 100644 --- a/src/arch/power/insts/misc.cc +++ b/src/arch/power/insts/misc.cc @@ -31,7 +31,7 @@ using namespace PowerISA; std::string -MiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MiscOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh index a1b57a4be..a81c623fa 100644 --- a/src/arch/power/insts/misc.hh +++ b/src/arch/power/insts/misc.hh @@ -40,15 +40,10 @@ namespace PowerISA class MiscOp : public PowerStaticInst { protected: - - /// Constructor - MiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) - : PowerStaticInst(mnem, _machInst, __opClass) - { - } + using PowerStaticInst::PowerStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } // namespace PowerISA diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc index 4b5c22987..97730b3b4 100644 --- a/src/arch/power/insts/static_inst.cc +++ b/src/arch/power/insts/static_inst.cc @@ -54,8 +54,8 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const } std::string -PowerStaticInst::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +PowerStaticInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh index 47c0d4831..dc53bc130 100644 --- a/src/arch/power/insts/static_inst.hh +++ b/src/arch/power/insts/static_inst.hh @@ -60,7 +60,7 @@ class PowerStaticInst : public StaticInst printReg(std::ostream &os, RegId reg) const; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; void advancePC(PowerISA::PCState &pcState) const override diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa index 5ef5e1b9b..fef28ce5b 100644 --- a/src/arch/power/isa/formats/unimp.isa +++ b/src/arch/power/isa/formats/unimp.isa @@ -55,7 +55,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -86,21 +86,21 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; output decoder {{ std::string - FailUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + FailUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } std::string - WarnUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + WarnUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa index 73c8c808b..d0f81f1ff 100644 --- a/src/arch/power/isa/formats/unknown.isa +++ b/src/arch/power/isa/formats/unknown.isa @@ -53,13 +53,14 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; output decoder {{ std::string - Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const + Unknown::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", "unknown", machInst, OPCODE, inst2string(machInst)); diff --git a/src/arch/power/linux/process.cc b/src/arch/power/linux/process.cc index 79c0a5eef..d613d52c1 100644 --- a/src/arch/power/linux/process.cc +++ b/src/arch/power/linux/process.cc @@ -51,19 +51,19 @@ class PowerLinuxObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { - if (obj_file->getArch() != ObjectFile::Power) + if (obj_file->getArch() != ::Loader::Power) return nullptr; auto opsys = obj_file->getOpSys(); - if (opsys == ObjectFile::UnknownOpSys) { + if (opsys == ::Loader::UnknownOpSys) { warn("Unknown operating system; assuming Linux."); - opsys = ObjectFile::Linux; + opsys = ::Loader::Linux; } - if (opsys != ObjectFile::Linux) + if (opsys != ::Loader::Linux) return nullptr; return new PowerLinuxProcess(params, obj_file); @@ -442,7 +442,7 @@ SyscallDescTable PowerLinuxProcess::syscallDescs = { }; PowerLinuxProcess::PowerLinuxProcess(ProcessParams * params, - ObjectFile *objFile) : + ::Loader::ObjectFile *objFile) : PowerProcess(params, objFile) {} diff --git a/src/arch/power/linux/process.hh b/src/arch/power/linux/process.hh index 857e883ac..a81edfb9d 100644 --- a/src/arch/power/linux/process.hh +++ b/src/arch/power/linux/process.hh @@ -38,7 +38,7 @@ class PowerLinuxProcess : public PowerProcess { public: - PowerLinuxProcess(ProcessParams * params, ObjectFile *objFile); + PowerLinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); void initState() override; diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index 914c99f66..01a2c9faf 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -46,7 +46,8 @@ using namespace std; using namespace PowerISA; -PowerProcess::PowerProcess(ProcessParams *params, ObjectFile *objFile) +PowerProcess::PowerProcess( + ProcessParams *params, ::Loader::ObjectFile *objFile) : Process(params, new EmulationPageTable(params->name, params->pid, PageBytes), objFile) @@ -99,7 +100,7 @@ PowerProcess::argsInit(int intSize, int pageSize) //Setup the auxilliary vectors. These will already have endian conversion. //Auxilliary vectors are loaded only for elf formatted executables. - ElfObject * elfObject = dynamic_cast(objFile); + auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile); if (elfObject) { uint32_t features = 0; diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh index cd973931b..7e4018308 100644 --- a/src/arch/power/process.hh +++ b/src/arch/power/process.hh @@ -37,12 +37,15 @@ #include "sim/process.hh" #include "sim/syscall_abi.hh" +namespace Loader +{ class ObjectFile; +} // namespace Loader; class PowerProcess : public Process { protected: - PowerProcess(ProcessParams * params, ObjectFile *objFile); + PowerProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); void initState() override; diff --git a/src/arch/riscv/bare_metal/fs_workload.cc b/src/arch/riscv/bare_metal/fs_workload.cc index 41fefe933..cea98e813 100644 --- a/src/arch/riscv/bare_metal/fs_workload.cc +++ b/src/arch/riscv/bare_metal/fs_workload.cc @@ -36,8 +36,8 @@ namespace RiscvISA { BareMetal::BareMetal(Params *p) : RiscvISA::FsWorkload(p), - bootloader(createObjectFile(p->bootloader)), - bootloaderSymtab(new SymbolTable) + bootloader(Loader::createObjectFile(p->bootloader)), + bootloaderSymtab(new Loader::SymbolTable) { fatal_if(!bootloader, "Could not load bootloader file %s.", p->bootloader); _resetVect = bootloader->entryPoint(); diff --git a/src/arch/riscv/bare_metal/fs_workload.hh b/src/arch/riscv/bare_metal/fs_workload.hh index 37bffcfe9..2e26ad1b2 100644 --- a/src/arch/riscv/bare_metal/fs_workload.hh +++ b/src/arch/riscv/bare_metal/fs_workload.hh @@ -38,8 +38,8 @@ namespace RiscvISA class BareMetal : public RiscvISA::FsWorkload { protected: - ObjectFile *bootloader; - SymbolTable *bootloaderSymtab; + Loader::ObjectFile *bootloader; + Loader::SymbolTable *bootloaderSymtab; public: typedef RiscvBareMetalParams Params; @@ -48,12 +48,8 @@ class BareMetal : public RiscvISA::FsWorkload void initState() override; - ObjectFile::Arch - getArch() const override - { - return bootloader->getArch(); - } - const SymbolTable * + Loader::Arch getArch() const override { return bootloader->getArch(); } + const Loader::SymbolTable * symtab(ThreadContext *tc) override { return bootloaderSymtab; diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc index 2f2259ab7..cf4b221b5 100644 --- a/src/arch/riscv/insts/amo.cc +++ b/src/arch/riscv/insts/amo.cc @@ -43,8 +43,9 @@ namespace RiscvISA { // memfence micro instruction -string MemFenceMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +MemFenceMicro::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; @@ -58,8 +59,9 @@ Fault MemFenceMicro::execute(ExecContext *xc, } // load-reserved -string LoadReserved::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +LoadReserved::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic; @@ -74,8 +76,9 @@ string LoadReserved::generateDisassembly(Addr pc, return ss.str(); } -string LoadReservedMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +LoadReservedMicro::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" @@ -84,8 +87,9 @@ string LoadReservedMicro::generateDisassembly(Addr pc, } // store-conditional -string StoreCond::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +StoreCond::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic; @@ -101,8 +105,9 @@ string StoreCond::generateDisassembly(Addr pc, return ss.str(); } -string StoreCondMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +StoreCondMicro::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " @@ -112,8 +117,9 @@ string StoreCondMicro::generateDisassembly(Addr pc, } // AMOs -string AtomicMemOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +AtomicMemOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic; @@ -129,8 +135,9 @@ string AtomicMemOp::generateDisassembly(Addr pc, return ss.str(); } -string AtomicMemOpMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const +string +AtomicMemOpMicro::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " diff --git a/src/arch/riscv/insts/amo.hh b/src/arch/riscv/insts/amo.hh index 432ae077e..e4f3a4e46 100644 --- a/src/arch/riscv/insts/amo.hh +++ b/src/arch/riscv/insts/amo.hh @@ -51,7 +51,7 @@ class MemFenceMicro : public RiscvMicroInst Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // load-reserved @@ -61,7 +61,7 @@ class LoadReserved : public RiscvMacroInst using RiscvMacroInst::RiscvMacroInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class LoadReservedMicro : public RiscvMicroInst @@ -71,7 +71,7 @@ class LoadReservedMicro : public RiscvMicroInst using RiscvMicroInst::RiscvMicroInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // store-cond @@ -81,7 +81,7 @@ class StoreCond : public RiscvMacroInst using RiscvMacroInst::RiscvMacroInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class StoreCondMicro : public RiscvMicroInst @@ -91,7 +91,7 @@ class StoreCondMicro : public RiscvMicroInst using RiscvMicroInst::RiscvMicroInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // AMOs @@ -101,7 +101,7 @@ class AtomicMemOp : public RiscvMacroInst using RiscvMacroInst::RiscvMacroInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class AtomicMemOpMicro : public RiscvMicroInst @@ -111,7 +111,7 @@ class AtomicMemOpMicro : public RiscvMicroInst using RiscvMicroInst::RiscvMicroInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** diff --git a/src/arch/riscv/insts/compressed.cc b/src/arch/riscv/insts/compressed.cc index 94b2574ba..65ccdf219 100644 --- a/src/arch/riscv/insts/compressed.cc +++ b/src/arch/riscv/insts/compressed.cc @@ -39,7 +39,8 @@ namespace RiscvISA { std::string -CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +CompRegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << diff --git a/src/arch/riscv/insts/compressed.hh b/src/arch/riscv/insts/compressed.hh index 837a09a51..b2f89dadd 100644 --- a/src/arch/riscv/insts/compressed.hh +++ b/src/arch/riscv/insts/compressed.hh @@ -47,7 +47,7 @@ class CompRegOp : public RiscvStaticInst using RiscvStaticInst::RiscvStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc index c4747ee65..d1dae7629 100644 --- a/src/arch/riscv/insts/mem.cc +++ b/src/arch/riscv/insts/mem.cc @@ -43,7 +43,7 @@ namespace RiscvISA { string -Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const +Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << @@ -52,7 +52,7 @@ Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const } string -Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const +Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " << diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh index 78eed19ad..0d4676c9f 100644 --- a/src/arch/riscv/insts/mem.hh +++ b/src/arch/riscv/insts/mem.hh @@ -56,7 +56,7 @@ class Load : public MemInst using MemInst::MemInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class Store : public MemInst @@ -65,7 +65,7 @@ class Store : public MemInst using MemInst::MemInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh index 47b11adc7..53fe6858d 100644 --- a/src/arch/riscv/insts/pseudo.hh +++ b/src/arch/riscv/insts/pseudo.hh @@ -42,7 +42,7 @@ class PseudoOp : public RiscvStaticInst using RiscvStaticInst::RiscvStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override + Addr pc, const Loader::SymbolTable *symtab) const override { return mnemonic; } @@ -50,4 +50,4 @@ class PseudoOp : public RiscvStaticInst } -#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__ \ No newline at end of file +#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__ diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index 1e7d22e49..0fcb2b589 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -42,7 +42,7 @@ namespace RiscvISA { string -RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << @@ -52,7 +52,7 @@ RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } string -CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "; diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh index a956d77e4..a68010e06 100644 --- a/src/arch/riscv/insts/standard.hh +++ b/src/arch/riscv/insts/standard.hh @@ -49,7 +49,7 @@ class RegOp : public RiscvStaticInst using RiscvStaticInst::RiscvStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -75,7 +75,8 @@ class SystemOp : public RiscvStaticInst using RiscvStaticInst::RiscvStaticInst; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { return mnemonic; } @@ -97,7 +98,7 @@ class CSROp : public RiscvStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh index 4b9f137ea..fe7825c6d 100644 --- a/src/arch/riscv/insts/unknown.hh +++ b/src/arch/riscv/insts/unknown.hh @@ -61,7 +61,8 @@ class Unknown : public RiscvStaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { return csprintf("unknown opcode %#02x", OPCODE); } diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 91b954583..9376d140d 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -124,8 +124,8 @@ def template CBasicDeclare {{ /// Constructor. %(class_name)s(MachInst machInst); Fault execute(ExecContext *, Trace::InstRecord *) const override; - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const override; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; }; }}; @@ -149,8 +149,8 @@ def template CBasicExecute {{ } std::string - %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + %(class_name)s::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::vector indices = {%(regs)s}; std::stringstream ss; diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index a6c6e1c62..04121513e 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -43,7 +43,7 @@ def template ImmDeclare {{ %(class_name)s(MachInst machInst); Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const override; + const Loader::SymbolTable *symtab) const override; }; }}; @@ -76,7 +76,7 @@ def template ImmExecute {{ std::string %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { std::vector indices = {%(regs)s}; std::stringstream ss; @@ -108,7 +108,7 @@ def template CILuiExecute {{ std::string %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { std::vector indices = {%(regs)s}; std::stringstream ss; @@ -142,7 +142,7 @@ def template FenceExecute {{ std::string %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { std::stringstream ss; ss << mnemonic; @@ -182,7 +182,8 @@ def template BranchDeclare {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override; + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; RiscvISA::PCState branchTarget(const RiscvISA::PCState &branchPC) const override; @@ -216,8 +217,8 @@ def template BranchExecute {{ } std::string - %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + %(class_name)s::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::vector indices = {%(regs)s}; std::stringstream ss; @@ -241,7 +242,8 @@ def template JumpDeclare {{ Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override; + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override; RiscvISA::PCState branchTarget(ThreadContext *tc) const override; @@ -277,8 +279,8 @@ def template JumpExecute {{ } std::string - %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + %(class_name)s::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::vector indices = {%(regs)s}; std::stringstream ss; diff --git a/src/arch/riscv/linux/process.cc b/src/arch/riscv/linux/process.cc index 45ee00f22..e70a07f9f 100644 --- a/src/arch/riscv/linux/process.cc +++ b/src/arch/riscv/linux/process.cc @@ -55,23 +55,23 @@ class RiscvLinuxObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { auto arch = obj_file->getArch(); auto opsys = obj_file->getOpSys(); - if (arch != ObjectFile::Riscv64 && arch != ObjectFile::Riscv32) + if (arch != ::Loader::Riscv64 && arch != ::Loader::Riscv32) return nullptr; - if (opsys == ObjectFile::UnknownOpSys) { + if (opsys == ::Loader::UnknownOpSys) { warn("Unknown operating system; assuming Linux."); - opsys = ObjectFile::Linux; + opsys = ::Loader::Linux; } - if (opsys != ObjectFile::Linux) + if (opsys != ::Loader::Linux) return nullptr; - if (arch == ObjectFile::Riscv64) + if (arch == ::Loader::Riscv64) return new RiscvLinuxProcess64(params, obj_file); else return new RiscvLinuxProcess32(params, obj_file); @@ -781,7 +781,7 @@ SyscallDescTable }; RiscvLinuxProcess64::RiscvLinuxProcess64(ProcessParams * params, - ObjectFile *objFile) : RiscvProcess64(params, objFile) + ::Loader::ObjectFile *objFile) : RiscvProcess64(params, objFile) {} void @@ -792,7 +792,7 @@ RiscvLinuxProcess64::syscall(ThreadContext *tc, Fault *fault) } RiscvLinuxProcess32::RiscvLinuxProcess32(ProcessParams * params, - ObjectFile *objFile) : RiscvProcess32(params, objFile) + ::Loader::ObjectFile *objFile) : RiscvProcess32(params, objFile) {} void diff --git a/src/arch/riscv/linux/process.hh b/src/arch/riscv/linux/process.hh index ec7d2673e..b553bef4f 100644 --- a/src/arch/riscv/linux/process.hh +++ b/src/arch/riscv/linux/process.hh @@ -42,7 +42,7 @@ class RiscvLinuxProcess64 : public RiscvProcess64 { public: /// Constructor. - RiscvLinuxProcess64(ProcessParams * params, ObjectFile *objFile); + RiscvLinuxProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile); /// The target system's hostname. static const char *hostname; @@ -60,7 +60,7 @@ class RiscvLinuxProcess32 : public RiscvProcess32 { public: /// Constructor. - RiscvLinuxProcess32(ProcessParams * params, ObjectFile *objFile); + RiscvLinuxProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile); /// The target system's hostname. static const char *hostname; diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index 402683627..9c0540012 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -57,7 +57,8 @@ using namespace std; using namespace RiscvISA; -RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) : +RiscvProcess::RiscvProcess(ProcessParams *params, + ::Loader::ObjectFile *objFile) : Process(params, new EmulationPageTable(params->name, params->pid, PageBytes), objFile) @@ -65,7 +66,8 @@ RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) : fatal_if(params->useArchPT, "Arch page tables not implemented."); } -RiscvProcess64::RiscvProcess64(ProcessParams *params, ObjectFile *objFile) : +RiscvProcess64::RiscvProcess64(ProcessParams *params, + ::Loader::ObjectFile *objFile) : RiscvProcess(params, objFile) { const Addr stack_base = 0x7FFFFFFFFFFFFFFFL; @@ -77,7 +79,8 @@ RiscvProcess64::RiscvProcess64(ProcessParams *params, ObjectFile *objFile) : max_stack_size, next_thread_stack_base, mmap_end); } -RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile *objFile) : +RiscvProcess32::RiscvProcess32(ProcessParams *params, + ::Loader::ObjectFile *objFile) : RiscvProcess(params, objFile) { const Addr stack_base = 0x7FFFFFFF; @@ -119,7 +122,7 @@ RiscvProcess::argsInit(int pageSize) const int RandomBytes = 16; const int addrSize = sizeof(IntType); - ElfObject* elfObject = dynamic_cast(objFile); + auto *elfObject = dynamic_cast<::Loader::ElfObject*>(objFile); memState->setStackMin(memState->getStackBase()); // Determine stack size and populate auxv diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh index b256962d3..05cde41fe 100644 --- a/src/arch/riscv/process.hh +++ b/src/arch/riscv/process.hh @@ -37,13 +37,17 @@ #include "sim/process.hh" #include "sim/syscall_abi.hh" +namespace Loader +{ class ObjectFile; +} // namespace Loader + class System; class RiscvProcess : public Process { protected: - RiscvProcess(ProcessParams * params, ObjectFile *objFile); + RiscvProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); template void argsInit(int pageSize); @@ -84,14 +88,14 @@ struct Result class RiscvProcess64 : public RiscvProcess { protected: - RiscvProcess64(ProcessParams * params, ObjectFile *objFile); + RiscvProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile); void initState() override; }; class RiscvProcess32 : public RiscvProcess { protected: - RiscvProcess32(ProcessParams * params, ObjectFile *objFile); + RiscvProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile); void initState() override; }; diff --git a/src/arch/sparc/fs_workload.hh b/src/arch/sparc/fs_workload.hh index d97b9225b..0323714e7 100644 --- a/src/arch/sparc/fs_workload.hh +++ b/src/arch/sparc/fs_workload.hh @@ -39,7 +39,7 @@ namespace SparcISA class FsWorkload : public Workload { protected: - SymbolTable defaultSymtab; + Loader::SymbolTable defaultSymtab; public: FsWorkload(SparcFsWorkloadParams *params) : Workload(params) {} @@ -52,9 +52,9 @@ class FsWorkload : public Workload getREDVector(0x001, pc, npc); return pc; } - ObjectFile::Arch getArch() const override { return ObjectFile::SPARC64; } + Loader::Arch getArch() const override { return Loader::SPARC64; } - const SymbolTable * + const Loader::SymbolTable * symtab(ThreadContext *tc) override { return &defaultSymtab; diff --git a/src/arch/sparc/insts/blockmem.cc b/src/arch/sparc/insts/blockmem.cc index 55762e5f8..6b6f2b0f2 100644 --- a/src/arch/sparc/insts/blockmem.cc +++ b/src/arch/sparc/insts/blockmem.cc @@ -32,7 +32,8 @@ namespace SparcISA { std::string -BlockMemMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BlockMemMicro::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; bool load = flags[IsLoad]; @@ -57,7 +58,8 @@ BlockMemMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -BlockMemImmMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BlockMemImmMicro::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; bool load = flags[IsLoad]; diff --git a/src/arch/sparc/insts/blockmem.hh b/src/arch/sparc/insts/blockmem.hh index a1e9a9f12..0528b6ad4 100644 --- a/src/arch/sparc/insts/blockmem.hh +++ b/src/arch/sparc/insts/blockmem.hh @@ -64,7 +64,7 @@ class BlockMemMicro : public SparcMicroInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; const int8_t offset; }; @@ -79,7 +79,7 @@ class BlockMemImmMicro : public BlockMemMicro {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; const int32_t imm; }; diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc index 426a59510..8ffa24165 100644 --- a/src/arch/sparc/insts/branch.cc +++ b/src/arch/sparc/insts/branch.cc @@ -41,7 +41,7 @@ template class BranchNBits<22>; template class BranchNBits<30>; std::string -Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const +Branch::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -55,7 +55,8 @@ Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -BranchImm13::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchImm13::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -72,7 +73,8 @@ BranchImm13::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -BranchDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +BranchDisp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; std::string symbol; diff --git a/src/arch/sparc/insts/branch.hh b/src/arch/sparc/insts/branch.hh index 26d13c729..03842bf26 100644 --- a/src/arch/sparc/insts/branch.hh +++ b/src/arch/sparc/insts/branch.hh @@ -48,7 +48,7 @@ class Branch : public SparcStaticInst using SparcStaticInst::SparcStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -63,7 +63,7 @@ class BranchDisp : public Branch {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; int32_t disp; }; @@ -110,7 +110,7 @@ class BranchImm13 : public Branch {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; int32_t imm; }; diff --git a/src/arch/sparc/insts/integer.cc b/src/arch/sparc/insts/integer.cc index 75916b56c..b92afe234 100644 --- a/src/arch/sparc/insts/integer.cc +++ b/src/arch/sparc/insts/integer.cc @@ -38,7 +38,7 @@ namespace SparcISA bool IntOp::printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symbab) const + const Loader::SymbolTable *symbab) const { if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) { printMnemonic(os, "mov"); @@ -52,7 +52,7 @@ IntOp::printPseudoOps(std::ostream &os, Addr pc, bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symbab) const + const Loader::SymbolTable *symbab) const { if (!std::strcmp(mnemonic, "or")) { if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) { @@ -76,7 +76,7 @@ IntOpImm::printPseudoOps(std::ostream &os, Addr pc, } std::string -IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -91,7 +91,7 @@ IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +IntOpImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -109,7 +109,7 @@ IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SetHi::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/sparc/insts/integer.hh b/src/arch/sparc/insts/integer.hh index c7ee6ca4d..1438cfd5e 100644 --- a/src/arch/sparc/insts/integer.hh +++ b/src/arch/sparc/insts/integer.hh @@ -48,10 +48,10 @@ class IntOp : public SparcStaticInst using SparcStaticInst::SparcStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; virtual bool printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; /** @@ -69,10 +69,10 @@ class IntOpImm : public IntOp int64_t imm; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; bool printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symtab) const override; + const Loader::SymbolTable *symtab) const override; }; /** @@ -121,7 +121,7 @@ class SetHi : public IntOpImm {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; } diff --git a/src/arch/sparc/insts/mem.cc b/src/arch/sparc/insts/mem.cc index c75bed8c0..594f08ba3 100644 --- a/src/arch/sparc/insts/mem.cc +++ b/src/arch/sparc/insts/mem.cc @@ -32,7 +32,7 @@ namespace SparcISA { std::string -Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const +Mem::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; bool load = flags[IsLoad]; @@ -59,7 +59,7 @@ Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -MemImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +MemImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; bool load = flags[IsLoad]; diff --git a/src/arch/sparc/insts/mem.hh b/src/arch/sparc/insts/mem.hh index 0170b1bcf..929fa94d1 100644 --- a/src/arch/sparc/insts/mem.hh +++ b/src/arch/sparc/insts/mem.hh @@ -48,7 +48,7 @@ class Mem : public SparcStaticInst using SparcStaticInst::SparcStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -64,7 +64,7 @@ class MemImm : public Mem {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; const int32_t imm; }; diff --git a/src/arch/sparc/insts/micro.cc b/src/arch/sparc/insts/micro.cc index 8c9c5a884..7bfeda1a6 100644 --- a/src/arch/sparc/insts/micro.cc +++ b/src/arch/sparc/insts/micro.cc @@ -32,7 +32,8 @@ namespace SparcISA { std::string -SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SparcMacroInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; printMnemonic(response, mnemonic); diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh index 99c9858eb..2cb2283b2 100644 --- a/src/arch/sparc/insts/micro.hh +++ b/src/arch/sparc/insts/micro.hh @@ -56,7 +56,7 @@ class SparcMacroInst : public SparcStaticInst } std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; StaticInstPtr *microops; diff --git a/src/arch/sparc/insts/nop.cc b/src/arch/sparc/insts/nop.cc index b2ee4a10f..990b93dcf 100644 --- a/src/arch/sparc/insts/nop.cc +++ b/src/arch/sparc/insts/nop.cc @@ -54,13 +54,14 @@ output header {{ } std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const override; + const Loader::SymbolTable *symtab) const override; }; }}; output decoder {{ - std::string Nop::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + Nop::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; printMnemonic(response, mnemonic); diff --git a/src/arch/sparc/insts/nop.hh b/src/arch/sparc/insts/nop.hh index 9b3d8ab9f..8bc100348 100644 --- a/src/arch/sparc/insts/nop.hh +++ b/src/arch/sparc/insts/nop.hh @@ -59,7 +59,8 @@ class Nop : public SparcStaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { std::stringstream response; printMnemonic(response, mnemonic); diff --git a/src/arch/sparc/insts/priv.cc b/src/arch/sparc/insts/priv.cc index b5481f60c..65113548f 100644 --- a/src/arch/sparc/insts/priv.cc +++ b/src/arch/sparc/insts/priv.cc @@ -33,7 +33,7 @@ namespace SparcISA { std::string -Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const +Priv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -43,7 +43,7 @@ Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const +RdPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -56,7 +56,7 @@ RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const +WrPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -76,7 +76,8 @@ WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string -WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +WrPrivImm::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/sparc/insts/priv.hh b/src/arch/sparc/insts/priv.hh index c2c10435b..f98cf6e4b 100644 --- a/src/arch/sparc/insts/priv.hh +++ b/src/arch/sparc/insts/priv.hh @@ -43,7 +43,7 @@ class Priv : public SparcStaticInst protected: using SparcStaticInst::SparcStaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; class PrivReg : public Priv @@ -64,7 +64,7 @@ class RdPriv : public PrivReg protected: using PrivReg::PrivReg; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; // This class is for instructions that explicitly write control @@ -74,7 +74,7 @@ class WrPriv : public PrivReg protected: using PrivReg::PrivReg; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; }; /** @@ -103,7 +103,7 @@ class WrPrivImm : public PrivImm {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; char const *regName; }; diff --git a/src/arch/sparc/insts/static_inst.cc b/src/arch/sparc/insts/static_inst.cc index 34a29775f..9e7bc6747 100644 --- a/src/arch/sparc/insts/static_inst.cc +++ b/src/arch/sparc/insts/static_inst.cc @@ -246,7 +246,8 @@ SparcStaticInst::printReg(std::ostream &os, RegId reg) } std::string -SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const +SparcStaticInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/sparc/insts/static_inst.hh b/src/arch/sparc/insts/static_inst.hh index 8eda23536..fcfb522cf 100644 --- a/src/arch/sparc/insts/static_inst.hh +++ b/src/arch/sparc/insts/static_inst.hh @@ -90,7 +90,7 @@ class SparcStaticInst : public StaticInst using StaticInst::StaticInst; std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; static void printMnemonic(std::ostream &os, const char *mnemonic); static void printReg(std::ostream &os, RegId reg); diff --git a/src/arch/sparc/insts/trap.cc b/src/arch/sparc/insts/trap.cc index fa003c81f..693ec8802 100644 --- a/src/arch/sparc/insts/trap.cc +++ b/src/arch/sparc/insts/trap.cc @@ -32,7 +32,7 @@ namespace SparcISA { std::string -Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const +Trap::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/sparc/insts/trap.hh b/src/arch/sparc/insts/trap.hh index ab3e3e66c..4f3c6def3 100644 --- a/src/arch/sparc/insts/trap.hh +++ b/src/arch/sparc/insts/trap.hh @@ -54,7 +54,7 @@ class Trap : public SparcStaticInst {} std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; + Addr pc, const Loader::SymbolTable *symtab) const override; int trapNum; }; @@ -65,7 +65,8 @@ class FpUnimpl : public SparcStaticInst using SparcStaticInst::SparcStaticInst; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { return mnemonic; } diff --git a/src/arch/sparc/insts/unimp.hh b/src/arch/sparc/insts/unimp.hh index 94964d23e..a1f6b805f 100644 --- a/src/arch/sparc/insts/unimp.hh +++ b/src/arch/sparc/insts/unimp.hh @@ -67,7 +67,8 @@ class FailUnimplemented : public SparcStaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { return csprintf("%-10s (unimplemented)", mnemonic); } @@ -106,7 +107,8 @@ class WarnUnimplemented : public SparcStaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { return csprintf("%-10s (unimplemented)", mnemonic); } diff --git a/src/arch/sparc/insts/unknown.hh b/src/arch/sparc/insts/unknown.hh index 994fe492b..f5c3b7318 100644 --- a/src/arch/sparc/insts/unknown.hh +++ b/src/arch/sparc/insts/unknown.hh @@ -53,7 +53,8 @@ class Unknown : public SparcStaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const override { return "Unknown instruction"; } diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index a9b3a0b7d..298822348 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -48,23 +48,23 @@ class SparcLinuxObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { auto arch = obj_file->getArch(); auto opsys = obj_file->getOpSys(); - if (arch != ObjectFile::SPARC64 && arch != ObjectFile::SPARC32) + if (arch != ::Loader::SPARC64 && arch != ::Loader::SPARC32) return nullptr; - if (opsys == ObjectFile::UnknownOpSys) { + if (opsys == ::Loader::UnknownOpSys) { warn("Unknown operating system; assuming Linux."); - opsys = ObjectFile::Linux; + opsys = ::Loader::Linux; } - if (opsys != ObjectFile::Linux) + if (opsys != ::Loader::Linux) return nullptr; - if (arch == ObjectFile::SPARC64) + if (arch == ::Loader::SPARC64) return new Sparc64LinuxProcess(params, obj_file); else return new Sparc32LinuxProcess(params, obj_file); @@ -76,7 +76,7 @@ SparcLinuxObjectFileLoader loader; } // anonymous namespace Sparc32LinuxProcess::Sparc32LinuxProcess(ProcessParams * params, - ObjectFile *objFile) + ::Loader::ObjectFile *objFile) : Sparc32Process(params, objFile) {} @@ -100,7 +100,7 @@ Sparc32LinuxProcess::handleTrap(int trapNum, ThreadContext *tc, Fault *fault) } Sparc64LinuxProcess::Sparc64LinuxProcess(ProcessParams * params, - ObjectFile *objFile) + ::Loader::ObjectFile *objFile) : Sparc64Process(params, objFile) {} diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index 45fcbd5d3..99c954789 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -54,7 +54,7 @@ class Sparc32LinuxProcess : public SparcLinuxProcess, public Sparc32Process { public: /// Constructor. - Sparc32LinuxProcess(ProcessParams * params, ObjectFile *objFile); + Sparc32LinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); void syscall(ThreadContext *tc, Fault *fault) override; @@ -66,7 +66,7 @@ class Sparc64LinuxProcess : public SparcLinuxProcess, public Sparc64Process { public: /// Constructor. - Sparc64LinuxProcess(ProcessParams * params, ObjectFile *objFile); + Sparc64LinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); void syscall(ThreadContext *tc, Fault *fault) override; diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 8dfe2e96f..3edbdf57d 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -52,8 +52,8 @@ const std::vector SparcProcess::SyscallABI::ArgumentRegs = { INTREG_O0, INTREG_O1, INTREG_O2, INTREG_O3, INTREG_O4, INTREG_O5 }; -SparcProcess::SparcProcess(ProcessParams *params, ObjectFile *objFile, - Addr _StackBias) +SparcProcess::SparcProcess(ProcessParams *params, + ::Loader::ObjectFile *objFile, Addr _StackBias) : Process(params, new EmulationPageTable(params->name, params->pid, PageBytes), objFile), @@ -220,7 +220,7 @@ SparcProcess::argsInit(int pageSize) // Setup the auxilliary vectors. These will already have endian conversion. // Auxilliary vectors are loaded only for elf formatted executables. - ElfObject * elfObject = dynamic_cast(objFile); + auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile); if (elfObject) { // Bits which describe the system hardware capabilities auxv.emplace_back(M5_AT_HWCAP, hwcap); diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh index d6fecfdec..bf9922402 100644 --- a/src/arch/sparc/process.hh +++ b/src/arch/sparc/process.hh @@ -50,7 +50,7 @@ class SparcProcess : public Process // The locations of the fill and spill handlers Addr fillStart, spillStart; - SparcProcess(ProcessParams * params, ObjectFile *objFile, + SparcProcess(ProcessParams * params, ::Loader::ObjectFile *objFile, Addr _StackBias); void initState() override; @@ -117,7 +117,7 @@ class Sparc32Process : public SparcProcess { protected: - Sparc32Process(ProcessParams * params, ObjectFile *objFile) + Sparc32Process(ProcessParams * params, ::Loader::ObjectFile *objFile) : SparcProcess(params, objFile, 0) { Addr brk_point = image.maxAddr(); @@ -182,7 +182,7 @@ class Sparc64Process : public SparcProcess { protected: - Sparc64Process(ProcessParams * params, ObjectFile *objFile) + Sparc64Process(ProcessParams * params, ::Loader::ObjectFile *objFile) : SparcProcess(params, objFile, 2047) { Addr brk_point = image.maxAddr(); diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index d5a7e08f5..f1a13caa7 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -48,15 +48,15 @@ class SparcSolarisObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { auto arch = obj_file->getArch(); auto opsys = obj_file->getOpSys(); - if (arch != ObjectFile::SPARC64 && arch != ObjectFile::SPARC32) + if (arch != ::Loader::SPARC64 && arch != ::Loader::SPARC32) return nullptr; - if (opsys != ObjectFile::Solaris) + if (opsys != ::Loader::Solaris) return nullptr; return new SparcSolarisProcess(params, obj_file); @@ -347,9 +347,9 @@ SyscallDescTable { 255, "umount2" } }; -SparcSolarisProcess::SparcSolarisProcess(ProcessParams * params, - ObjectFile *objFile) - : Sparc64Process(params, objFile) +SparcSolarisProcess::SparcSolarisProcess(ProcessParams *params, + ::Loader::ObjectFile *objFile) : + Sparc64Process(params, objFile) {} void diff --git a/src/arch/sparc/solaris/process.hh b/src/arch/sparc/solaris/process.hh index f9a638611..2f218bb56 100644 --- a/src/arch/sparc/solaris/process.hh +++ b/src/arch/sparc/solaris/process.hh @@ -41,7 +41,7 @@ class SparcSolarisProcess : public Sparc64Process { public: /// Constructor. - SparcSolarisProcess(ProcessParams * params, ObjectFile *objFile); + SparcSolarisProcess(ProcessParams * params, ::Loader::ObjectFile *objFile); /// The target system's hostname. static const char *hostname; diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index ca890c3a3..98bd10755 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -168,7 +168,8 @@ namespace X86ISA } else { panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s", modeStr, addr, tc->pcState().pc(), - inst->disassemble(tc->pcState().pc(), debugSymbolTable)); + inst->disassemble(tc->pcState().pc(), + Loader::debugSymbolTable)); } } } diff --git a/src/arch/x86/fs_workload.cc b/src/arch/x86/fs_workload.cc index 6ad42db04..3f46ebaf3 100644 --- a/src/arch/x86/fs_workload.cc +++ b/src/arch/x86/fs_workload.cc @@ -121,7 +121,7 @@ FsWorkload::initState() fatal_if(!kernelObj, "No kernel to load."); - fatal_if(kernelObj->getArch() == ObjectFile::I386, + fatal_if(kernelObj->getArch() == Loader::I386, "Loading a 32 bit x86 kernel is not supported."); ThreadContext *tc = system->threadContexts[0]; diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh index da768d84a..30a8d4fd1 100644 --- a/src/arch/x86/insts/macroop.hh +++ b/src/arch/x86/insts/macroop.hh @@ -82,7 +82,7 @@ class MacroopBase : public X86StaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { return mnemonic; } diff --git a/src/arch/x86/insts/microfpop.cc b/src/arch/x86/insts/microfpop.cc index 2a2182baa..0ff9c58ff 100644 --- a/src/arch/x86/insts/microfpop.cc +++ b/src/arch/x86/insts/microfpop.cc @@ -51,8 +51,9 @@ namespace X86ISA } */ - std::string FpOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + FpOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh index 9eacf246e..d13af317b 100644 --- a/src/arch/x86/insts/microfpop.hh +++ b/src/arch/x86/insts/microfpop.hh @@ -74,8 +74,8 @@ namespace X86ISA bool subtract = false) const; bool checkCondition(uint64_t flags) const;*/ - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; } diff --git a/src/arch/x86/insts/microldstop.cc b/src/arch/x86/insts/microldstop.cc index 9ec213288..8a17f2b26 100644 --- a/src/arch/x86/insts/microldstop.cc +++ b/src/arch/x86/insts/microldstop.cc @@ -42,8 +42,9 @@ namespace X86ISA { - std::string LdStOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + LdStOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -58,8 +59,9 @@ namespace X86ISA return response.str(); } - std::string LdStSplitOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + LdStSplitOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh index 3b4074115..6994584c8 100644 --- a/src/arch/x86/insts/microldstop.hh +++ b/src/arch/x86/insts/microldstop.hh @@ -112,8 +112,8 @@ namespace X86ISA { } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; /** @@ -146,8 +146,8 @@ namespace X86ISA { } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; } diff --git a/src/arch/x86/insts/micromediaop.cc b/src/arch/x86/insts/micromediaop.cc index b2311de1b..0e7dbad8f 100644 --- a/src/arch/x86/insts/micromediaop.cc +++ b/src/arch/x86/insts/micromediaop.cc @@ -34,8 +34,9 @@ namespace X86ISA { - std::string MediaOpReg::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + MediaOpReg::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -48,8 +49,9 @@ namespace X86ISA return response.str(); } - std::string MediaOpImm::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + MediaOpImm::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh index cac5b4b70..79b1158a2 100644 --- a/src/arch/x86/insts/micromediaop.hh +++ b/src/arch/x86/insts/micromediaop.hh @@ -104,7 +104,7 @@ namespace X86ISA {} std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; class MediaOpImm : public MediaOpBase @@ -125,7 +125,7 @@ namespace X86ISA {} std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; } diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh index e209e9cd0..151de448a 100644 --- a/src/arch/x86/insts/microop.hh +++ b/src/arch/x86/insts/microop.hh @@ -109,8 +109,8 @@ namespace X86ISA } } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index ed0ba279c..32b27140e 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -76,8 +76,9 @@ namespace X86ISA return flags; } - std::string RegOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + RegOp::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -90,8 +91,9 @@ namespace X86ISA return response.str(); } - std::string RegOpImm::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + RegOpImm::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh index 1f0bfe3e1..b1d103968 100644 --- a/src/arch/x86/insts/microregop.hh +++ b/src/arch/x86/insts/microregop.hh @@ -92,8 +92,8 @@ namespace X86ISA { } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; class RegOpImm : public RegOpBase @@ -114,8 +114,8 @@ namespace X86ISA { } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; }; } diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index f8d989fe6..f8e137b5c 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -264,8 +264,9 @@ namespace X86ISA os << "]"; } - std::string X86StaticInst::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + X86StaticInst::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh index 8a7a11226..2bf93b6b1 100644 --- a/src/arch/x86/insts/static_inst.hh +++ b/src/arch/x86/insts/static_inst.hh @@ -86,8 +86,8 @@ namespace X86ISA { } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; void printMnemonic(std::ostream &os, const char * mnemonic) const; void printMnemonic(std::ostream &os, const char * instMnemonic, diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa index 288393a18..f4ed015f7 100644 --- a/src/arch/x86/isa/formats/cpuid.isa +++ b/src/arch/x86/isa/formats/cpuid.isa @@ -48,13 +48,14 @@ output header {{ } std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; output decoder {{ - std::string CPUIDInst::generateDisassembly(Addr PC, - const SymbolTable *symtab) const + std::string + CPUIDInst::generateDisassembly( + Addr PC, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa index 1dbf89731..0733a2aab 100644 --- a/src/arch/x86/isa/formats/monitor_mwait.isa +++ b/src/arch/x86/isa/formats/monitor_mwait.isa @@ -15,13 +15,14 @@ output header {{ { } std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; output decoder {{ - std::string MonitorInst::generateDisassembly(Addr PC, - const SymbolTable *symtab) const + std::string + MonitorInst::generateDisassembly( + Addr PC, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -93,13 +94,14 @@ output header {{ } std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; output decoder {{ - std::string MwaitInst::generateDisassembly(Addr PC, - const SymbolTable *symtab) const + std::string + MwaitInst::generateDisassembly( + Addr PC, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/formats/nop.isa b/src/arch/x86/isa/formats/nop.isa index c81e618d0..1a708d175 100644 --- a/src/arch/x86/isa/formats/nop.isa +++ b/src/arch/x86/isa/formats/nop.isa @@ -54,13 +54,13 @@ output header {{ } std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; output decoder {{ std::string NopInst::generateDisassembly(Addr PC, - const SymbolTable *symtab) const + const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa index 98d9758bd..f728d7d96 100644 --- a/src/arch/x86/isa/formats/syscall.isa +++ b/src/arch/x86/isa/formats/syscall.isa @@ -54,13 +54,14 @@ output header {{ } std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; output decoder {{ - std::string SyscallInst::generateDisassembly(Addr PC, - const SymbolTable *symtab) const + std::string + SyscallInst::generateDisassembly( + Addr PC, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa index 1ddfa40c5..b3e21ac3c 100644 --- a/src/arch/x86/isa/formats/unimp.isa +++ b/src/arch/x86/isa/formats/unimp.isa @@ -63,7 +63,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const; }; /** @@ -79,12 +79,12 @@ output header {{ { private: /// Have we warned on this instruction yet? - mutable bool warned; + mutable bool warned = false; public: /// Constructor WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst) - : X86ISA::X86StaticInst(_mnemonic, _machInst, No_OpClass), warned(false) + : X86ISA::X86StaticInst(_mnemonic, _machInst, No_OpClass) { // don't call execute() (which panics) if we're on a // speculative path @@ -94,21 +94,21 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const; }; }}; output decoder {{ std::string - FailUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + FailUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } std::string - WarnUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + WarnUnimplemented::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { return csprintf("%-10s (unimplemented)", mnemonic); } diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa index 83511469f..b24928db8 100644 --- a/src/arch/x86/isa/formats/unknown.isa +++ b/src/arch/x86/isa/formats/unknown.isa @@ -42,43 +42,44 @@ // output header {{ - /** - * Class for Unknown/Illegal instructions - */ - class Unknown : public X86ISA::X86StaticInst - { - public: + /** + * Class for Unknown/Illegal instructions + */ + class Unknown : public X86ISA::X86StaticInst + { + public: - // Constructor - Unknown(ExtMachInst _machInst) : - X86ISA::X86StaticInst("unknown", _machInst, No_OpClass) - { - } + // Constructor + Unknown(ExtMachInst _machInst) : + X86ISA::X86StaticInst("unknown", _machInst, No_OpClass) + { + } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const; - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; - }; + }; }}; output decoder {{ - std::string Unknown::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - return "Unknown instruction"; - } + std::string + Unknown::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const + { + return "Unknown instruction"; + } }}; output exec {{ - Fault Unknown::execute(ExecContext *xc, - Trace::InstRecord *traceData) const - { - return std::make_shared(); - } + Fault + Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const + { + return std::make_shared(); + } }}; def format Unknown() {{ - decode_block = 'return new Unknown(machInst);\n' + decode_block = 'return new Unknown(machInst);\n' }}; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 8ca176ce8..2e67d1b9c 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -42,30 +42,29 @@ // Execute method for macroops. def template MacroExecPanic {{ - Fault execute(ExecContext *, Trace::InstRecord *) const - { - panic("Tried to execute macroop directly!"); - return NoFault; - } + Fault execute(ExecContext *, Trace::InstRecord *) const + { + panic("Tried to execute macroop directly!"); + return NoFault; + } }}; output header {{ + // Base class for combinationally generated macroops + class Macroop : public X86ISA::MacroopBase + { + public: + Macroop(const char *mnem, ExtMachInst _machInst, + uint32_t _numMicroops, X86ISA::EmulEnv _env) + : MacroopBase(mnem, _machInst, _numMicroops, _env) + {} - // Base class for combinationally generated macroops - class Macroop : public X86ISA::MacroopBase + Fault + execute(ExecContext *, Trace::InstRecord *) const { - public: - Macroop(const char *mnem, ExtMachInst _machInst, - uint32_t _numMicroops, X86ISA::EmulEnv _env) - : MacroopBase(mnem, _machInst, _numMicroops, _env) - {} - - Fault - execute(ExecContext *, Trace::InstRecord *) const - { - panic("Tried to execute macroop directly!"); - } - }; + panic("Tried to execute macroop directly!"); + } + }; }}; ////////////////////////////////////////////////////////////////////////////// @@ -76,29 +75,29 @@ output header {{ // Basic instruction class declaration template. def template MacroDeclare {{ - namespace X86Macroop + namespace X86Macroop + { + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s { - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - private: - %(declareLabels)s - public: - // Constructor. - %(class_name)s(ExtMachInst machInst, X86ISA::EmulEnv _env); + private: + %(declareLabels)s + public: + // Constructor. + %(class_name)s(ExtMachInst machInst, X86ISA::EmulEnv _env); - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - } + std::string generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const; + }; + } }}; def template MacroDisassembly {{ std::string - X86Macroop::%(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + X86Macroop::%(class_name)s::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream out; out << mnemonic << "\t"; diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index d488cdb60..af2975ac5 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -57,7 +57,7 @@ output header {{ } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index 44ec8499a..1fdbcf4bc 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -61,7 +61,7 @@ def template MicroLimmOpDeclare {{ RegIndex foldOBit; std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; public: %(class_name)s(ExtMachInst _machInst, @@ -74,8 +74,9 @@ def template MicroLimmOpDeclare {{ }}; def template MicroLimmOpDisassembly {{ - std::string %(class_name)s::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + %(class_name)s::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa index 66b863921..80c92b01d 100644 --- a/src/arch/x86/isa/microops/seqop.isa +++ b/src/arch/x86/isa/microops/seqop.isa @@ -50,7 +50,7 @@ output header {{ uint16_t _target, uint8_t _cc); std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; @@ -104,8 +104,9 @@ def template SeqOpConstructor {{ }}; output decoder {{ - std::string SeqOpBase::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + SeqOpBase::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 55de0f3c2..f5e5a7742 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -52,7 +52,7 @@ output header {{ uint64_t setFlags, Fault _fault, uint8_t _cc); std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; class MicroHalt : public X86ISA::X86MicroopBase @@ -70,7 +70,7 @@ output header {{ Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + const Loader::SymbolTable *symtab) const; }; }}; @@ -130,8 +130,9 @@ def template MicroFaultConstructor {{ }}; output decoder {{ - std::string MicroFaultBase::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + MicroFaultBase::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; @@ -144,8 +145,9 @@ output decoder {{ return response.str(); } - std::string MicroHalt::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + MicroHalt::generateDisassembly( + Addr pc, const Loader::SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc index cd76224ce..6b50dbf5b 100644 --- a/src/arch/x86/linux/process.cc +++ b/src/arch/x86/linux/process.cc @@ -60,23 +60,23 @@ class X86LinuxObjectFileLoader : public Process::Loader { public: Process * - load(ProcessParams *params, ObjectFile *obj_file) override + load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override { auto arch = obj_file->getArch(); auto opsys = obj_file->getOpSys(); - if (arch != ObjectFile::X86_64 && arch != ObjectFile::I386) + if (arch != ::Loader::X86_64 && arch != ::Loader::I386) return nullptr; - if (opsys == ObjectFile::UnknownOpSys) { + if (opsys == ::Loader::UnknownOpSys) { warn("Unknown operating system; assuming Linux."); - opsys = ObjectFile::Linux; + opsys = ::Loader::Linux; } - if (opsys != ObjectFile::Linux) + if (opsys != ::Loader::Linux) return nullptr; - if (arch == ObjectFile::X86_64) + if (arch == ::Loader::X86_64) return new X86_64LinuxProcess(params, obj_file); else return new I386LinuxProcess(params, obj_file); diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 3743049b2..f377e2a2b 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -102,11 +102,11 @@ typedef MultiLevelPageTable, LongModePTE<29, 21>, LongModePTE<20, 12> > ArchPageTable; -X86Process::X86Process(ProcessParams *params, ObjectFile *objFile) : +X86Process::X86Process(ProcessParams *params, ::Loader::ObjectFile *objFile) : Process(params, params->useArchPT ? static_cast( - new ArchPageTable(params->name, params->pid, - params->system, PageBytes)) : + new ArchPageTable(params->name, params->pid, + params->system, PageBytes)) : new EmulationPageTable(params->name, params->pid, PageBytes), objFile) @@ -121,7 +121,8 @@ void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, *process = *this; } -X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile) : +X86_64Process::X86_64Process(ProcessParams *params, + ::Loader::ObjectFile *objFile) : X86Process(params, objFile) { vsyscallPage.base = 0xffffffffff600000ULL; @@ -141,7 +142,8 @@ X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile) : } -I386Process::I386Process(ProcessParams *params, ObjectFile *objFile) : +I386Process::I386Process(ProcessParams *params, + ::Loader::ObjectFile *objFile) : X86Process(params, objFile) { if (kvmInSE) @@ -788,7 +790,7 @@ X86Process::argsInit(int pageSize, // conversion. Auxiliary vectors are loaded only for elf formatted // executables; the auxv is responsible for passing information from // the OS to the interpreter. - ElfObject * elfObject = dynamic_cast(objFile); + auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile); if (elfObject) { uint64_t features = X86_OnboardFPU | diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh index 3edc218fd..039e55a65 100644 --- a/src/arch/x86/process.hh +++ b/src/arch/x86/process.hh @@ -61,7 +61,7 @@ namespace X86ISA Addr _gdtStart; Addr _gdtSize; - X86Process(ProcessParams * params, ObjectFile *objFile); + X86Process(ProcessParams *params, ::Loader::ObjectFile *objFile); template void argsInit(int pageSize, @@ -118,7 +118,7 @@ namespace X86ISA VSyscallPage vsyscallPage; public: - X86_64Process(ProcessParams *params, ObjectFile *objFile); + X86_64Process(ProcessParams *params, ::Loader::ObjectFile *objFile); void argsInit(int pageSize); void initState() override; @@ -155,7 +155,7 @@ namespace X86ISA VSyscallPage vsyscallPage; public: - I386Process(ProcessParams *params, ObjectFile *objFile); + I386Process(ProcessParams *params, ::Loader::ObjectFile *objFile); void argsInit(int pageSize); void initState() override; diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc index 677ab65d5..a7c548ea2 100644 --- a/src/arch/x86/stacktrace.cc +++ b/src/arch/x86/stacktrace.cc @@ -45,7 +45,7 @@ static int32_t readSymbol(ThreadContext *tc, const std::string name) { PortProxy &vp = tc->getVirtProxy(); - const SymbolTable *symtab = tc->getSystemPtr()->workload->symtab(tc); + const auto *symtab = tc->getSystemPtr()->workload->symtab(tc); Addr addr; if (!symtab->findAddress(name, addr)) @@ -189,7 +189,7 @@ void StackTrace::dump() { StringWrap name(tc->getCpuPtr()->name()); - const SymbolTable *symtab = tc->getSystemPtr()->workload->symtab(tc); + const auto *symtab = tc->getSystemPtr()->workload->symtab(tc); DPRINTFN("------ Stack ------\n"); diff --git a/src/base/cp_annotate.cc b/src/base/cp_annotate.cc index 59c32ab83..c886e3970 100644 --- a/src/base/cp_annotate.cc +++ b/src/base/cp_annotate.cc @@ -113,14 +113,14 @@ CPA::CPA(Params *p) i = p->user_apps.begin(); while (i != p->user_apps.end()) { - ObjectFile *of = createObjectFile(*i); + auto *of = createObjectFile(*i); string sf; if (!of) fatal("Couldn't load symbols from file: %s\n", *i); sf = *i; sf.erase(0, sf.rfind('/') + 1);; DPRINTFN("file %s short: %s\n", *i, sf); - userApp[sf] = new SymbolTable; + userApp[sf] = new Loader::SymbolTable; bool result1 = of->loadGlobalSymbols(userApp[sf]); bool result2 = of->loadLocalSymbols(userApp[sf]); if (!result1 || !result2) @@ -163,7 +163,7 @@ CPA::swSmBegin(ThreadContext *tc, Addr sm_string, int32_t sm_id, int32_t flags) Addr junk; char sm[50]; if (!TheISA::inUserMode(tc)) - debugSymbolTable->findNearestSymbol( + Loader::debugSymbolTable->findNearestSymbol( tc->readIntReg(ReturnAddressReg), st, junk); tc->getVirtProxy().readString(sm, sm_string, 50); @@ -337,7 +337,7 @@ CPA::swAutoBegin(ThreadContext *tc, Addr next_pc) Addr sym_addr = 0; if (!TheISA::inUserMode(tc)) { - debugSymbolTable->findNearestSymbol(next_pc, sym, sym_addr); + Loader::debugSymbolTable->findNearestSymbol(next_pc, sym, sym_addr); } else { Linux::ThreadInfo ti(tc); string app = ti.curTaskName(); @@ -390,7 +390,7 @@ CPA::swEnd(ThreadContext *tc) std::string st; Addr junk; if (!TheISA::inUserMode(tc)) - debugSymbolTable->findNearestSymbol( + Loader::debugSymbolTable->findNearestSymbol( tc->readIntReg(ReturnAddressReg), st, junk); System *sys = tc->getSystemPtr(); StringWrap name(sys->name()); diff --git a/src/base/cp_annotate.hh b/src/base/cp_annotate.hh index a3f1560d1..a33780320 100644 --- a/src/base/cp_annotate.hh +++ b/src/base/cp_annotate.hh @@ -417,7 +417,7 @@ class CPA : SimObject static CPA *_cpa; - std::map userApp; + std::map userApp; public: static CPA *cpa() { return _cpa; } diff --git a/src/base/loader/dtb_file.cc b/src/base/loader/dtb_file.cc index b290e5a3b..7405cfe7b 100644 --- a/src/base/loader/dtb_file.cc +++ b/src/base/loader/dtb_file.cc @@ -37,6 +37,9 @@ #include "libfdt.h" #include "sim/byteswap.hh" +namespace Loader +{ + DtbFile::DtbFile(const std::string &filename) : ImageFile(ImageFileDataPtr(new ImageFileData(filename))) { @@ -152,3 +155,5 @@ DtbFile::buildImage() const else return {{ "data", 0, fileData, length }}; } + +} // namespace Loader diff --git a/src/base/loader/dtb_file.hh b/src/base/loader/dtb_file.hh index a65f547f7..3a9d72453 100644 --- a/src/base/loader/dtb_file.hh +++ b/src/base/loader/dtb_file.hh @@ -31,6 +31,9 @@ #include "base/loader/image_file.hh" +namespace Loader +{ + /** @file * This implements an image file format to support loading * and modifying flattened device tree blobs for use with @@ -67,4 +70,6 @@ class DtbFile : public ImageFile MemoryImage buildImage() const override; }; +} // namespace Loader + #endif //__BASE_LOADER_DTB_FILE_HH__ diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 076cb9466..8876a8735 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -57,6 +57,9 @@ #include "gelf.h" #include "sim/byteswap.hh" +namespace Loader +{ + ObjectFile * ElfObjectFormat::load(ImageFileDataPtr ifd) { @@ -455,3 +458,5 @@ ElfObject::updateBias(Addr bias_addr) // Patch segments with the bias_addr. image.offset(bias_addr); } + +} // namespace Loader diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh index 8bda988f0..f96c26caf 100644 --- a/src/base/loader/elf_object.hh +++ b/src/base/loader/elf_object.hh @@ -47,6 +47,9 @@ #include "base/loader/object_file.hh" #include "gelf.h" +namespace Loader +{ + class ElfObjectFormat : public ObjectFileFormat { public: @@ -137,4 +140,6 @@ class ElfObject : public ObjectFile */ void setInterpDir(const std::string &dirname); +} // namespace Loader + #endif // __BASE_LOADER_ELF_OBJECT_HH__ diff --git a/src/base/loader/image_file.hh b/src/base/loader/image_file.hh index 194f63cb1..9894f8212 100644 --- a/src/base/loader/image_file.hh +++ b/src/base/loader/image_file.hh @@ -35,6 +35,9 @@ #include "base/loader/image_file_data.hh" #include "base/loader/memory_image.hh" +namespace Loader +{ + class ImageFile { protected: @@ -46,4 +49,6 @@ class ImageFile virtual MemoryImage buildImage() const = 0; }; +} // namespace Loader + #endif // __BASE_LOADER_IMAGE_FILE_HH__ diff --git a/src/base/loader/image_file_data.cc b/src/base/loader/image_file_data.cc index 3d78ada4f..a94d3c6e5 100644 --- a/src/base/loader/image_file_data.cc +++ b/src/base/loader/image_file_data.cc @@ -39,6 +39,9 @@ #include "base/logging.hh" +namespace Loader +{ + static bool hasGzipMagic(int fd) { @@ -125,3 +128,5 @@ ImageFileData::~ImageFileData() { munmap((void *)_data, _len); } + +} // namespace Loader diff --git a/src/base/loader/image_file_data.hh b/src/base/loader/image_file_data.hh index e484f713e..5745348f0 100644 --- a/src/base/loader/image_file_data.hh +++ b/src/base/loader/image_file_data.hh @@ -33,6 +33,9 @@ #include #include +namespace Loader +{ + class ImageFileData { private: @@ -51,4 +54,6 @@ class ImageFileData typedef std::shared_ptr ImageFileDataPtr; +} // namespace Loader + #endif // __BASE_LOADER_IMAGE_FILE_DATA_HH__ diff --git a/src/base/loader/image_file_data.test.cc b/src/base/loader/image_file_data.test.cc index 16ad04e4b..0ca96ee60 100644 --- a/src/base/loader/image_file_data.test.cc +++ b/src/base/loader/image_file_data.test.cc @@ -35,6 +35,8 @@ #include "base/loader/image_file_data.hh" #include "base/loader/small_image_file.test.hh" +using namespace Loader; + TEST(ImageFileDataTest, SimpleImage) { /* diff --git a/src/base/loader/memory_image.cc b/src/base/loader/memory_image.cc index 4a5b1f2de..feedac6d0 100644 --- a/src/base/loader/memory_image.cc +++ b/src/base/loader/memory_image.cc @@ -29,6 +29,9 @@ #include "base/loader/memory_image.hh" #include "mem/port_proxy.hh" +namespace Loader +{ + bool MemoryImage::writeSegment(const Segment &seg, const PortProxy &proxy) const { @@ -59,3 +62,5 @@ MemoryImage::move(std::function mapper) seg.base = mapper(seg.base); return *this; } + +} // namespace Loader diff --git a/src/base/loader/memory_image.hh b/src/base/loader/memory_image.hh index c92ca4fe8..e0e1e630f 100644 --- a/src/base/loader/memory_image.hh +++ b/src/base/loader/memory_image.hh @@ -42,6 +42,9 @@ class PortProxy; +namespace Loader +{ + class MemoryImage { public: @@ -162,5 +165,6 @@ operator << (std::ostream &os, const MemoryImage::Segment &seg) return os; } +} // namespace Loader #endif // __BASE_LOADER_MEMORY_IMAGE_HH__ diff --git a/src/base/loader/object_file.cc b/src/base/loader/object_file.cc index 45a3781eb..12e560675 100644 --- a/src/base/loader/object_file.cc +++ b/src/base/loader/object_file.cc @@ -32,14 +32,14 @@ #include #include "base/loader/raw_image.hh" -#include "base/loader/symtab.hh" -#include "mem/port_proxy.hh" -using namespace std; +namespace Loader +{ ObjectFile::ObjectFile(ImageFileDataPtr ifd) : ImageFile(ifd) {} -namespace { +namespace +{ typedef std::vector ObjectFileFormatList; @@ -73,3 +73,5 @@ createObjectFile(const std::string &fname, bool raw) return nullptr; } + +} // namespace Loader diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh index 045fd3873..cdd82c3d2 100644 --- a/src/base/loader/object_file.hh +++ b/src/base/loader/object_file.hh @@ -37,36 +37,37 @@ #include "base/logging.hh" #include "base/types.hh" -class SymbolTable; - -class ObjectFile : public ImageFile +namespace Loader { - public: - enum Arch { - UnknownArch, - SPARC64, - SPARC32, - Mips, - X86_64, - I386, - Arm64, - Arm, - Thumb, - Power, - Riscv64, - Riscv32 - }; +enum Arch { + UnknownArch, + SPARC64, + SPARC32, + Mips, + X86_64, + I386, + Arm64, + Arm, + Thumb, + Power, + Riscv64, + Riscv32 +}; - enum OpSys { - UnknownOpSys, - Tru64, - Linux, - Solaris, - LinuxArmOABI, - FreeBSD - }; +enum OpSys { + UnknownOpSys, + Tru64, + Linux, + Solaris, + LinuxArmOABI, + FreeBSD +}; + +class SymbolTable; +class ObjectFile : public ImageFile +{ protected: Arch arch = UnknownArch; OpSys opSys = UnknownOpSys; @@ -141,4 +142,6 @@ class ObjectFileFormat ObjectFile *createObjectFile(const std::string &fname, bool raw=false); +} // namespace Loader + #endif // __BASE_LOADER_OBJECT_FILE_HH__ diff --git a/src/base/loader/raw_image.hh b/src/base/loader/raw_image.hh index 56c18552a..40f768571 100644 --- a/src/base/loader/raw_image.hh +++ b/src/base/loader/raw_image.hh @@ -31,6 +31,9 @@ #include "base/loader/object_file.hh" +namespace Loader +{ + class RawImage: public ObjectFile { public: @@ -47,6 +50,6 @@ class RawImage: public ObjectFile } }; - +} // namespace Loader #endif // __BASE_LOADER_RAW_IMAGE_HH__ diff --git a/src/base/loader/symtab.cc b/src/base/loader/symtab.cc index b040e3b6d..9e0f1f68c 100644 --- a/src/base/loader/symtab.cc +++ b/src/base/loader/symtab.cc @@ -40,6 +40,9 @@ using namespace std; +namespace Loader +{ + SymbolTable *debugSymbolTable = NULL; void @@ -136,3 +139,5 @@ SymbolTable::unserialize(const string &base, CheckpointIn &cp) insert(addr, symbol); } } + +} // namespace Loader diff --git a/src/base/loader/symtab.hh b/src/base/loader/symtab.hh index 9bd025297..b09d8545f 100644 --- a/src/base/loader/symtab.hh +++ b/src/base/loader/symtab.hh @@ -36,6 +36,9 @@ #include "base/types.hh" #include "sim/serialize.hh" +namespace Loader +{ + class SymbolTable { public: @@ -172,4 +175,6 @@ class SymbolTable /// global one has worked well enough. extern SymbolTable *debugSymbolTable; +} // namespace Loader + #endif // __SYMTAB_HH__ diff --git a/src/cpu/base.cc b/src/cpu/base.cc index c0788db96..d9cbc1c35 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -751,16 +751,15 @@ bool AddressMonitor::doMonitor(PacketPtr pkt) { void BaseCPU::traceFunctionsInternal(Addr pc) { - if (!debugSymbolTable) + if (!Loader::debugSymbolTable) return; // if pc enters different function, print new function symbol and // update saved range. Otherwise do nothing. if (pc < currentFunctionStart || pc >= currentFunctionEnd) { string sym_str; - bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, - currentFunctionStart, - currentFunctionEnd); + bool found = Loader::debugSymbolTable->findNearestSymbol( + pc, sym_str, currentFunctionStart, currentFunctionEnd); if (!found) { // no symbol found: use addr as label diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index ad9b4c369..06154daa7 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -79,9 +79,10 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) std::string sym_str; Addr sym_addr; Addr cur_pc = pc.instAddr(); - if (debugSymbolTable && Debug::ExecSymbol && + if (Loader::debugSymbolTable && Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) && - debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { + Loader::debugSymbolTable->findNearestSymbol( + cur_pc, sym_str, sym_addr)) { if (cur_pc != sym_addr) sym_str += csprintf("+%d",cur_pc - sym_addr); outs << "@" << sym_str; @@ -102,7 +103,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) // outs << setw(26) << left; - outs << inst->disassemble(cur_pc, debugSymbolTable); + outs << inst->disassemble(cur_pc, Loader::debugSymbolTable); if (ran) { outs << " : "; diff --git a/src/cpu/profile.cc b/src/cpu/profile.cc index 9f3045691..aa2cff892 100644 --- a/src/cpu/profile.cc +++ b/src/cpu/profile.cc @@ -45,8 +45,8 @@ ProfileNode::ProfileNode() { } void -ProfileNode::dump(const string &symbol, uint64_t id, const SymbolTable *symtab, - ostream &os) const +ProfileNode::dump(const string &symbol, uint64_t id, + const Loader::SymbolTable *symtab, ostream &os) const { ccprintf(os, "%#x %s %d ", id, symbol, count); ChildList::const_iterator i, end = children.end(); @@ -83,7 +83,7 @@ ProfileNode::clear() i->second->clear(); } -FunctionProfile::FunctionProfile(const SymbolTable *_symtab) +FunctionProfile::FunctionProfile(const Loader::SymbolTable *_symtab) : reset(0), symtab(_symtab) { reset = new MakeCallback(this); diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh index 4d3a0b896..0eb245545 100644 --- a/src/cpu/profile.hh +++ b/src/cpu/profile.hh @@ -53,7 +53,7 @@ class ProfileNode ProfileNode(); void dump(const std::string &symbol, uint64_t id, - const SymbolTable *symtab, std::ostream &os) const; + const Loader::SymbolTable *symtab, std::ostream &os) const; void clear(); }; @@ -62,13 +62,13 @@ class FunctionProfile { private: Callback *reset; - const SymbolTable *symtab; + const Loader::SymbolTable *symtab; ProfileNode top; std::map pc_count; TheISA::StackTrace trace; public: - FunctionProfile(const SymbolTable *symtab); + FunctionProfile(const Loader::SymbolTable *symtab); ~FunctionProfile(); ProfileNode *consume(ThreadContext *tc, const StaticInstPtr &inst); diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index 3e93ea454..f21d41bbc 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -55,7 +55,8 @@ class NopStaticInst : public StaticInst } std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const override + generateDisassembly(Addr pc, + const Loader::SymbolTable *symtab) const override { return mnemonic; } @@ -117,7 +118,7 @@ StaticInst::branchTarget(ThreadContext *tc) const } const string & -StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const +StaticInst::disassemble(Addr pc, const Loader::SymbolTable *symtab) const { if (!cachedDisassembly) cachedDisassembly = new string(generateDisassembly(pc, symtab)); diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 1467673e9..b523ef935 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -64,11 +64,15 @@ class Packet; class ExecContext; +namespace Loader +{ class SymbolTable; +} // namespace Loader -namespace Trace { - class InstRecord; -} +namespace Trace +{ +class InstRecord; +} // namespace Trace /** * Base, ISA-independent static instruction class. @@ -251,7 +255,7 @@ class StaticInst : public RefCounted, public StaticInstFlags * Internal function to generate disassembly string. */ virtual std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; + generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const = 0; /// Constructor. /// It's important to initialize everything here to a sane @@ -322,7 +326,7 @@ class StaticInst : public RefCounted, public StaticInstFlags * should not be cached, this function should be overridden directly. */ virtual const std::string &disassemble(Addr pc, - const SymbolTable *symtab = 0) const; + const Loader::SymbolTable *symtab=nullptr) const; /** * Print a separator separated list of this instruction's set flag diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc index 548ae0fe0..9286ab071 100644 --- a/src/kern/linux/helpers.cc +++ b/src/kern/linux/helpers.cc @@ -93,7 +93,7 @@ Linux::dumpDmesg(ThreadContext *tc, std::ostream &os) { System *system = tc->getSystemPtr(); const ByteOrder bo = system->getGuestByteOrder(); - const SymbolTable *symtab = system->workload->symtab(tc); + const auto *symtab = system->workload->symtab(tc); PortProxy &proxy = tc->getVirtProxy(); Addr addr_lb = 0, addr_lb_len = 0, addr_first = 0, addr_next = 0; diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index aa800113b..9323f61e8 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -77,13 +77,13 @@ AbstractMemory::initState() if (file == "") return; - auto *object = createObjectFile(file, true); + auto *object = Loader::createObjectFile(file, true); fatal_if(!object, "%s: Could not load %s.", name(), file); - panic_if(!object->loadGlobalSymbols(debugSymbolTable), + panic_if(!object->loadGlobalSymbols(Loader::debugSymbolTable), "%s: Could not load symbols from %s.", name(), file); - MemoryImage image = object->buildImage(); + Loader::MemoryImage image = object->buildImage(); AddrRange image_range(image.minAddr(), image.maxAddr()); if (!range.contains(image_range.start())) { diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc index 44e18331a..4b7defed3 100644 --- a/src/python/pybind11/core.cc +++ b/src/python/pybind11/core.cc @@ -203,7 +203,7 @@ init_loader(py::module &m_native) { py::module m = m_native.def_submodule("loader"); - m.def("setInterpDir", &setInterpDir); + m.def("setInterpDir", &Loader::setInterpDir); } void diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc index 3d9a5dc48..f107d696e 100644 --- a/src/sim/kernel_workload.cc +++ b/src/sim/kernel_workload.cc @@ -33,12 +33,12 @@ KernelWorkload::KernelWorkload(const Params &p) : Workload(&p), _params(p), _loadAddrMask(p.load_addr_mask), _loadAddrOffset(p.load_addr_offset), - kernelSymtab(new SymbolTable), commandLine(p.command_line) + kernelSymtab(new Loader::SymbolTable), commandLine(p.command_line) { - if (!debugSymbolTable) - debugSymbolTable = new SymbolTable; + if (!Loader::debugSymbolTable) + Loader::debugSymbolTable = new Loader::SymbolTable; - kernelObj = createObjectFile(params().object_file); + kernelObj = Loader::createObjectFile(params().object_file); inform("kernel located at: %s", params().object_file); fatal_if(!kernelObj, @@ -66,10 +66,10 @@ KernelWorkload::KernelWorkload(const Params &p) : Workload(&p), _params(p), fatal_if(!kernelObj->loadLocalSymbols(kernelSymtab), "Could not load kernel local symbols."); - fatal_if(!kernelObj->loadGlobalSymbols(debugSymbolTable), + fatal_if(!kernelObj->loadGlobalSymbols(Loader::debugSymbolTable), "Could not load kernel symbols."); - fatal_if(!kernelObj->loadLocalSymbols(debugSymbolTable), + fatal_if(!kernelObj->loadLocalSymbols(Loader::debugSymbolTable), "Could not load kernel local symbols."); // Loading only needs to happen once and after memory system is @@ -83,7 +83,7 @@ KernelWorkload::KernelWorkload(const Params &p) : Workload(&p), _params(p), for (int ker_idx = 0; ker_idx < p.extras.size(); ker_idx++) { const std::string &obj_name = p.extras[ker_idx]; const bool raw = extras_addrs[ker_idx] != MaxAddr; - ObjectFile *obj = createObjectFile(obj_name, raw); + auto *obj = Loader::createObjectFile(obj_name, raw); fatal_if(!obj, "Failed to build additional kernel object '%s'.\n", obj_name); extras.push_back(obj); diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh index b45a0d98c..972a539b1 100644 --- a/src/sim/kernel_workload.hh +++ b/src/sim/kernel_workload.hh @@ -32,11 +32,11 @@ #include #include "base/loader/object_file.hh" +#include "base/loader/symtab.hh" #include "base/types.hh" #include "params/KernelWorkload.hh" #include "sim/workload.hh" -class SymbolTable; class System; class KernelWorkload : public Workload @@ -47,7 +47,7 @@ class KernelWorkload : public Workload protected: const Params &_params; - MemoryImage image; + Loader::MemoryImage image; /** Mask that should be anded for binary/symbol loading. * This allows one two different OS requirements for the same ISA to be @@ -66,10 +66,10 @@ class KernelWorkload : public Workload Addr _start, _end; - std::vector extras; + std::vector extras; - ObjectFile *kernelObj = nullptr; - SymbolTable *kernelSymtab = nullptr; + Loader::ObjectFile *kernelObj = nullptr; + Loader::SymbolTable *kernelSymtab = nullptr; const std::string commandLine; @@ -85,8 +85,13 @@ class KernelWorkload : public Workload ~KernelWorkload(); Addr getEntry() const override { return kernelObj->entryPoint(); } - ObjectFile::Arch getArch() const override { return kernelObj->getArch(); } - const SymbolTable * + Loader::Arch + getArch() const override + { + return kernelObj->getArch(); + } + + const Loader::SymbolTable * symtab(ThreadContext *tc) override { return kernelSymtab; diff --git a/src/sim/process.cc b/src/sim/process.cc index 36f413f0c..a55362d0a 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -90,7 +90,7 @@ Process::Loader::Loader() } Process * -Process::tryLoaders(ProcessParams *params, ObjectFile *obj_file) +Process::tryLoaders(ProcessParams *params, ::Loader::ObjectFile *obj_file) { for (auto &loader: process_loaders()) { Process *p = loader->load(params, obj_file); @@ -110,7 +110,7 @@ normalize(std::string& directory) } Process::Process(ProcessParams *params, EmulationPageTable *pTable, - ObjectFile *obj_file) + ::Loader::ObjectFile *obj_file) : SimObject(params), system(params->system), useArchPT(params->useArchPT), kvmInSE(params->kvmInSE), @@ -155,13 +155,13 @@ Process::Process(ProcessParams *params, EmulationPageTable *pTable, image = objFile->buildImage(); - if (!debugSymbolTable) { - debugSymbolTable = new SymbolTable(); - if (!objFile->loadGlobalSymbols(debugSymbolTable) || - !objFile->loadLocalSymbols(debugSymbolTable) || - !objFile->loadWeakSymbols(debugSymbolTable)) { - delete debugSymbolTable; - debugSymbolTable = nullptr; + if (!::Loader::debugSymbolTable) { + ::Loader::debugSymbolTable = new ::Loader::SymbolTable(); + if (!objFile->loadGlobalSymbols(::Loader::debugSymbolTable) || + !objFile->loadLocalSymbols(::Loader::debugSymbolTable) || + !objFile->loadWeakSymbols(::Loader::debugSymbolTable)) { + delete ::Loader::debugSymbolTable; + ::Loader::debugSymbolTable = nullptr; } } } @@ -442,7 +442,7 @@ Process::checkPathRedirect(const std::string &filename) void Process::updateBias() { - ObjectFile *interp = objFile->getInterpreter(); + auto *interp = objFile->getInterpreter(); if (!interp || !interp->relocatable()) return; @@ -465,7 +465,7 @@ Process::updateBias() interp->updateBias(ld_bias); } -ObjectFile * +Loader::ObjectFile * Process::getInterpreter() { return objFile->getInterpreter(); @@ -474,7 +474,7 @@ Process::getInterpreter() Addr Process::getBias() { - ObjectFile *interp = getInterpreter(); + auto *interp = getInterpreter(); return interp ? interp->bias() : objFile->bias(); } @@ -482,7 +482,7 @@ Process::getBias() Addr Process::getStartPC() { - ObjectFile *interp = getInterpreter(); + auto *interp = getInterpreter(); return interp ? interp->entryPoint() : objFile->entryPoint(); } @@ -523,7 +523,7 @@ ProcessParams::create() executable = cmd[0]; } - ObjectFile *obj_file = createObjectFile(executable); + auto *obj_file = Loader::createObjectFile(executable); fatal_if(!obj_file, "Cannot load object file %s.", executable); Process *process = Process::tryLoaders(this, obj_file); diff --git a/src/sim/process.hh b/src/sim/process.hh index 350057e0f..0add01ab9 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -48,10 +48,14 @@ #include "sim/mem_state.hh" #include "sim/sim_object.hh" +namespace Loader +{ +class ObjectFile; +} // namespace Loader + struct ProcessParams; class EmulatedDriver; -class ObjectFile; class EmulationPageTable; class SyscallDesc; class SyscallReturn; @@ -62,7 +66,7 @@ class Process : public SimObject { public: Process(ProcessParams *params, EmulationPageTable *pTable, - ObjectFile *obj_file); + ::Loader::ObjectFile *obj_file); void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; @@ -99,7 +103,7 @@ class Process : public SimObject void updateBias(); Addr getBias(); Addr getStartPC(); - ObjectFile *getInterpreter(); + ::Loader::ObjectFile *getInterpreter(); // override of virtual SimObject method: register statistics void regStats() override; @@ -197,16 +201,18 @@ class Process : public SimObject * error like file IO errors, etc., those should fail non-silently * with a panic or fail as normal. */ - virtual Process *load(ProcessParams *params, ObjectFile *obj_file) = 0; + virtual Process *load(ProcessParams *params, + ::Loader::ObjectFile *obj_file) = 0; }; // Try all the Loader instance's "load" methods one by one until one is // successful. If none are, complain and fail. - static Process *tryLoaders(ProcessParams *params, ObjectFile *obj_file); + static Process *tryLoaders(ProcessParams *params, + ::Loader::ObjectFile *obj_file); - ObjectFile *objFile; - MemoryImage image; - MemoryImage interpImage; + ::Loader::ObjectFile *objFile; + ::Loader::MemoryImage image; + ::Loader::MemoryImage interpImage; std::vector argv; std::vector envp; std::string executable; diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 802b30423..a450bd885 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -240,7 +240,7 @@ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); tc->getSystemPtr()->workload->insertSymbol(addr, symbol); - debugSymbolTable->insert(addr,symbol); + Loader::debugSymbolTable->insert(addr, symbol); } uint64_t diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index e5444b1d8..5bd9f54f3 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -1713,13 +1713,13 @@ mmapFunc(SyscallDesc *desc, ThreadContext *tc, if (p->interpImage.contains(tc->pcState().instAddr())) { std::shared_ptr fdep = (*p->fds)[tgt_fd]; auto ffdp = std::dynamic_pointer_cast(fdep); - ObjectFile *lib = createObjectFile(p->checkPathRedirect( + auto *lib = Loader::createObjectFile(p->checkPathRedirect( ffdp->getFileName())); DPRINTF_SYSCALL(Verbose, "Loading symbols from %s\n", ffdp->getFileName()); if (lib) { - lib->loadAllSymbols(debugSymbolTable, + lib->loadAllSymbols(Loader::debugSymbolTable, lib->buildImage().minAddr(), start); } } diff --git a/src/sim/system.hh b/src/sim/system.hh index 7d7f9647a..fa59765ba 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -67,7 +67,6 @@ class BaseRemoteGDB; class KvmVM; -class ObjectFile; class ThreadContext; class System : public SimObject, public PCEventScope diff --git a/src/sim/workload.hh b/src/sim/workload.hh index bde138ef4..ca2dffbd4 100644 --- a/src/sim/workload.hh +++ b/src/sim/workload.hh @@ -47,9 +47,9 @@ class Workload : public SimObject System *system = nullptr; virtual Addr getEntry() const = 0; - virtual ObjectFile::Arch getArch() const = 0; + virtual Loader::Arch getArch() const = 0; - virtual const SymbolTable *symtab(ThreadContext *tc) = 0; + virtual const Loader::SymbolTable *symtab(ThreadContext *tc) = 0; virtual bool insertSymbol(Addr address, const std::string &symbol) = 0; /** @{ */ @@ -67,7 +67,7 @@ class Workload : public SimObject */ template T * - addFuncEvent(const SymbolTable *symtab, const char *lbl, + addFuncEvent(const Loader::SymbolTable *symtab, const char *lbl, const std::string &desc, Args... args) { Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning @@ -82,14 +82,14 @@ class Workload : public SimObject template T * - addFuncEvent(const SymbolTable *symtab, const char *lbl) + addFuncEvent(const Loader::SymbolTable *symtab, const char *lbl) { return addFuncEvent(symtab, lbl, lbl); } template T * - addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, + addFuncEventOrPanic(const Loader::SymbolTable *symtab, const char *lbl, Args... args) { T *e = addFuncEvent(symtab, lbl, std::forward(args)...); diff --git a/src/unittest/nmtest.cc b/src/unittest/nmtest.cc index 8524d516c..f444a90d4 100644 --- a/src/unittest/nmtest.cc +++ b/src/unittest/nmtest.cc @@ -43,17 +43,19 @@ main(int argc, char *argv[]) if (argc != 2 && argc != 3) panic("usage: %s \n", argv[0]); - ObjectFile *obj = createObjectFile(argv[1]); + auto *obj = Loader::createObjectFile(argv[1]); if (!obj) panic("file not found\n"); - SymbolTable symtab; + Loader::SymbolTable symtab; obj->loadGlobalSymbols(&symtab); obj->loadLocalSymbols(&symtab); if (argc == 2) { - SymbolTable::ATable::const_iterator i = symtab.getAddrTable().begin(); - SymbolTable::ATable::const_iterator end = symtab.getAddrTable().end(); + Loader::SymbolTable::ATable::const_iterator i = + symtab.getAddrTable().begin(); + Loader::SymbolTable::ATable::const_iterator end = + symtab.getAddrTable().end(); while (i != end) { cprintf("%#x %s\n", i->first, i->second); ++i; diff --git a/src/unittest/symtest.cc b/src/unittest/symtest.cc index 7534529d0..fd006b482 100644 --- a/src/unittest/symtest.cc +++ b/src/unittest/symtest.cc @@ -46,7 +46,7 @@ usage(const char *progname) int main(int argc, char *argv[]) { - SymbolTable symtab; + Loader::SymbolTable symtab; if (argc != 3) usage(argv[0]); -- 2.30.2