From 988d47af8533a0c7728095862dbc6a7311c1f8b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 17:50:30 -0700 Subject: [PATCH] tests: read +/xilinx/cell_sim.v before xilinx_dsp test --- tests/arch/xilinx/xilinx_dsp.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys index 3b9f52930..59d8296ab 100644 --- a/tests/arch/xilinx/xilinx_dsp.ys +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -8,4 +8,5 @@ assign o4 = a * b; DSP48E1 m3 (.A(a), .B(b), .P(o5)); endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v xilinx_dsp -- 2.30.2