From 989ca6851e7b1ff835aa6e3f84f6988c93e6698b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Jul 2018 12:13:38 +0100
Subject: [PATCH] auto-generate bus.bsv with new GPIO/MUX configs

---
 src/bsv/bus_transactors.py  | 14 +++----------
 src/bsv/pinmux_generator.py | 42 ++++++++++++++++++++++++++++++++++---
 src/parse.py                |  4 ++--
 3 files changed, 44 insertions(+), 16 deletions(-)

diff --git a/src/bsv/bus_transactors.py b/src/bsv/bus_transactors.py
index b4ebefd..8c73cdc 100644
--- a/src/bsv/bus_transactors.py
+++ b/src/bsv/bus_transactors.py
@@ -18,22 +18,14 @@ package gpio_instance;
 
   // instantiation template
     interface GPIO_real;
-    interface PeripheralSide peripheral_side;
-    interface GPIO_config#(32) bankA_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankA_slave;
-    interface GPIO_config#(15) bankB_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankB_slave;
-
-    interface MUX_config#(32) muxbankA_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxbankA_slave;
-    interface MUX_config#(15) muxbankB_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxbankB_slave;
+        interface PeripheralSide peripheral_side;
+{1}
     endinterface
   (*synthesize*)
   module mkgpio_real(GPIO_real);
     Ifc_pinmux pinmux <-mkpinmux;
     // gpio/mux declarations
-{3}
+{0}
     interface peripheral_side=pinmux.peripheral_side;
   endmodule
 endpackage
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index bfcc09e..9fe54eb 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -303,9 +303,45 @@ endpackage
 
 def write_bvp(bvp, p, ifaces):
     # ######## Generate bus transactors ################
+    gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config\n;' \
+              '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
+    muxcfg  = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
+              '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
+
+    gpiodec = '\tGPIO#({0} mygpio{1} <- mkgpio();'
+    muxdec  = '\tMUX#({0} mymux{1} <- mkgpio();'
+    gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
+              '\tinterface bank{0}A_slave=mygpio{0}.axi_slave;'
+    muxifc  = '\tinterface muxb{0}_config=mymux{0}.pad_config;\n' \
+              '\tinterface muxb{0}A_slave=mymux{0}.axi_slave;'
     with open(bvp, 'w') as bsv_file:
-        gpiodecl = '// TODO'
-        bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH,
+        # assume here that all muxes have a 1:1 gpio
+        cfg = []
+        decl = []
+        idec = []
+        iks = ifaces.keys()
+        iks.sort()
+        for iname in iks:
+            if not iname.startswith('gpio'): # TODO: declare other interfaces
+                continue
+            bank = iname[4:]
+            ifc = ifaces[iname]
+            npins = len(ifc.pinspecs)
+            cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
                                         0, # USERSPACE
-                                        gpiodecl))
+                                        bank, npins))
+            cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
+                                        0, # USERSPACE
+                                        bank, npins))
+            decl.append(gpiodec.format(npins, bank))
+            decl.append(muxdec .format(npins, bank))
+            idec.append(gpioifc.format(bank))
+            idec.append(muxifc.format(bank))
+        print dir(ifaces)
+        print ifaces.items()
+        print dir(ifaces['gpioa'])
+        print ifaces['gpioa'].pinspecs
+        gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
+        gpiocfg = '\n'.join(cfg) 
+        bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
     # ##################################################
diff --git a/src/parse.py b/src/parse.py
index 3d508d6..42886a6 100644
--- a/src/parse.py
+++ b/src/parse.py
@@ -14,8 +14,8 @@ class Parse(object):
     N_IO = 0
     N_MUX_IO = 0
     Addressing = 'WORD'
-    ADDR_WIDTH = 32
-    DATA_WIDTH = 32
+    ADDR_WIDTH = 32 # TODO parameterise
+    DATA_WIDTH = 32 # TODO parameterise
     # ================ #
 
     # Generating the number of bits for memory map #
-- 
2.30.2