From 98a049728b91940c4caac28a64c8235fef9d3a07 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 9 May 2021 19:00:50 +0200 Subject: [PATCH] move skeleton to elaborate --- src/soc/fu/ldst/loadstore.py | 40 ++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index bec6536d..77e11a6a 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -99,26 +99,6 @@ class LoadStore1(PortInterfaceBase): #self.nia = Signal(64) #self.srr1 = Signal(16) - # fsm skeleton - with m.Switch(self.state): - with m.Case(State.IDLE): - pass - with m.Case(State.SECOND_REQ): - # req.eq(1); - # v.state.eq(ACK_WAIT) - # v.last_dword.eq(0); - pass - with m.Case(State.ACK_WAIT): - pass - with m.Case(State.MMU_LOOKUP): - pass - with m.Case(State.TLBIE_WAIT): - pass - with m.Case(State.FINISH_LFS): - pass - with m.Case(State.COMPLETE): - pass - def set_wr_addr(self, m, addr, mask, misalign): m.d.comb += self.load.eq(0) # store operation @@ -194,6 +174,26 @@ class LoadStore1(PortInterfaceBase): # temp vars d_in, d_out, l_out, dbus = self.d_in, self.d_out, self.l_out, self.dbus + # fsm skeleton + with m.Switch(self.state): + with m.Case(State.IDLE): + pass + with m.Case(State.SECOND_REQ): + # req.eq(1); + # v.state.eq(ACK_WAIT) + # v.last_dword.eq(0); + pass + with m.Case(State.ACK_WAIT): + pass + with m.Case(State.MMU_LOOKUP): + pass + with m.Case(State.TLBIE_WAIT): + pass + with m.Case(State.FINISH_LFS): + pass + with m.Case(State.COMPLETE): + pass + with m.If(d_out.error): with m.If(d_out.cache_paradox): sync += self.derror.eq(1) -- 2.30.2