From 98a2492290be3d6d9a73a75935c9105e6b5b3f31 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Fri, 12 May 2017 01:24:48 +0200 Subject: [PATCH] ac_surface: use radeon_info from ac_gpu_info MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák --- src/amd/common/ac_surface.c | 47 ++++++++++--------- src/amd/common/ac_surface.h | 11 ++--- .../winsys/amdgpu/drm/amdgpu_surface.c | 6 +-- src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 2 +- 4 files changed, 31 insertions(+), 35 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 0bcbc61815c..609bf5c86a0 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -26,7 +26,9 @@ */ #include "ac_surface.h" +#include "amd_family.h" #include "amdgpu_id.h" +#include "ac_gpu_info.h" #include "util/macros.h" #include "util/u_math.h" @@ -147,8 +149,8 @@ static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInpu return ADDR_OK; } -ADDR_HANDLE amdgpu_addr_create(enum radeon_family family, - const struct amdgpu_gpu_info *info) +ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, + const struct amdgpu_gpu_info *amdinfo) { ADDR_CREATE_INPUT addrCreateInput = {0}; ADDR_CREATE_OUTPUT addrCreateOutput = {0}; @@ -159,10 +161,10 @@ ADDR_HANDLE amdgpu_addr_create(enum radeon_family family, addrCreateInput.size = sizeof(ADDR_CREATE_INPUT); addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT); - regValue.gbAddrConfig = info->gb_addr_cfg; + regValue.gbAddrConfig = amdinfo->gb_addr_cfg; createFlags.value = 0; - addrlib_family_rev_id(family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision); + addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision); if (addrCreateInput.chipFamily == FAMILY_UNKNOWN) return NULL; @@ -170,18 +172,18 @@ ADDR_HANDLE amdgpu_addr_create(enum radeon_family family, addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND; regValue.blockVarSizeLog2 = 0; } else { - regValue.noOfBanks = info->mc_arb_ramcfg & 0x3; - regValue.noOfRanks = (info->mc_arb_ramcfg & 0x4) >> 2; + regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3; + regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2; - regValue.backendDisables = info->enabled_rb_pipes_mask; - regValue.pTileConfig = info->gb_tile_mode; - regValue.noOfEntries = ARRAY_SIZE(info->gb_tile_mode); + regValue.backendDisables = amdinfo->enabled_rb_pipes_mask; + regValue.pTileConfig = amdinfo->gb_tile_mode; + regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); if (addrCreateInput.chipFamily == FAMILY_SI) { regValue.pMacroTileConfig = NULL; regValue.noOfMacroEntries = 0; } else { - regValue.pMacroTileConfig = info->gb_macro_tile_mode; - regValue.noOfMacroEntries = ARRAY_SIZE(info->gb_macro_tile_mode); + regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode; + regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode); } createFlags.useTileIndex = 1; @@ -359,11 +361,11 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07) static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, - const struct amdgpu_gpu_info *amdinfo) + const struct radeon_info *info) { - uint32_t tile_mode = amdinfo->gb_tile_mode[surf->u.legacy.tiling_index[0]]; + uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]]; - if (amdinfo->family_id >= AMDGPU_FAMILY_CI) + if (info->chip_class >= CIK) surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); else surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode); @@ -390,6 +392,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf) * blk_w, blk_h, bpe, flags. */ static int gfx6_compute_surface(ADDR_HANDLE addrlib, + const struct radeon_info *info, const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf) @@ -495,7 +498,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, * driver team). */ AddrSurfInfoIn.flags.dccCompatible = - config->chip_class >= VI && + info->chip_class >= VI && !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && AddrDccIn.numSamples <= 1 && @@ -544,7 +547,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); - if (config->chip_class == SI) { + if (info->chip_class == SI) { if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) { if (surf->bpe == 2) AddrSurfInfoIn.tileIndex = 11; /* 16bpp */ @@ -590,7 +593,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, if (level == 0) { surf->surf_alignment = AddrSurfInfoOut.baseAlign; surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1; - gfx6_set_micro_tile_mode(surf, config->amdinfo); + gfx6_set_micro_tile_mode(surf, info); /* For 2D modes only. */ if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { @@ -644,8 +647,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, */ if (surf->dcc_size && config->info.levels > 1) { surf->dcc_size = align64(surf->surf_size >> 8, - config->pipe_interleave_bytes * - config->num_tile_pipes); + info->pipe_interleave_bytes * + info->num_tile_pipes); } /* Make sure HTILE covers the whole miptree, because the shader reads @@ -1038,7 +1041,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, return 0; } -int ac_compute_surface(ADDR_HANDLE addrlib, +int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf) @@ -1049,8 +1052,8 @@ int ac_compute_surface(ADDR_HANDLE addrlib, if (r) return r; - if (config->chip_class >= GFX9) + if (info->chip_class >= GFX9) return gfx9_compute_surface(addrlib, config, mode, surf); else - return gfx6_compute_surface(addrlib, config, mode, surf); + return gfx6_compute_surface(addrlib, info, config, mode, surf); } diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 73649c76a10..9905be916ba 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -34,6 +34,7 @@ typedef void* ADDR_HANDLE; struct amdgpu_gpu_info; +struct radeon_info; #define RADEON_SURF_MAX_LEVELS 15 @@ -195,16 +196,12 @@ struct ac_surf_config { struct ac_surf_info info; unsigned is_3d : 1; unsigned is_cube : 1; - enum chip_class chip_class : 4; - unsigned num_tile_pipes; - unsigned pipe_interleave_bytes; - const struct amdgpu_gpu_info *amdinfo; }; -ADDR_HANDLE amdgpu_addr_create(enum radeon_family family, - const struct amdgpu_gpu_info *info); +ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, + const struct amdgpu_gpu_info *amdinfo); -int ac_compute_surface(ADDR_HANDLE addrlib, +int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, const struct ac_surf_config * config, enum radeon_surf_mode mode, struct radeon_surf *surf); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index cd403f5bfb0..1a2b7c4afb3 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -92,12 +92,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, config.info.levels = tex->last_level + 1; config.is_3d = !!(tex->target == PIPE_TEXTURE_3D); config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE); - config.chip_class = ws->info.chip_class; - config.num_tile_pipes = ws->info.num_tile_pipes; - config.pipe_interleave_bytes = ws->info.pipe_interleave_bytes; - config.amdinfo = &ws->amdinfo; - return ac_compute_surface(ws->addrlib, &config, mode, surf); + return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf); } void amdgpu_surface_init_functions(struct amdgpu_winsys *ws) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index 4398bbc074e..0430c7ec6ac 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -59,7 +59,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd) goto fail; } - ws->addrlib = amdgpu_addr_create(ws->info.family, &ws->amdinfo); + ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo); if (!ws->addrlib) { fprintf(stderr, "amdgpu: Cannot create addrlib.\n"); goto fail; -- 2.30.2