From 98b7299502503e5869e16170d0a541a9deb67e42 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 13:53:30 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 27a164ff6..0e4082c8d 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -544,8 +544,16 @@ OpenCAPI, assuming that the map of edges in any given arbitrary data graph could be kept by the main CPU in-memory, could distribute and delegate a limited-capability deterministic but most importantly *data-dependent* node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier). -Thanks to the OpenCAPI Standard, many of the nightmare problems +Thanks to the OpenCAPI Standard, which takes care of Virtual Memory +abstraction, locking, and cache-coherency, many of the nightmare problems of other more explicit parallel processing paradigms disappear. +The similarity to ZOLC should not have gone unnoticed: where ZOLC +has nested conditional for-loops Extra-V appears to have just the +one conditional for-loop, but the key strategically-crucial +part of this multi-faceted puzzle is that due to the deterministic and +coherent nature of Extra-V, the processing of the loops is +*embedded right next to the memory* + **Snitch** -- 2.30.2