From 98c27eee12ba30403df0cf3f84361fb05de5b2de Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 23 Dec 2020 12:49:34 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 0053bf3af..52c24e59b 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -207,7 +207,7 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2. -## RM-2P-2S1D/1S2D +## RM-2P-2S1D/1S2D/3S The primary purpose for this encoding is for Twin Predication on LOAD and STORE operations. see [[sv/ldst]] for detailed anslysis. @@ -225,6 +225,8 @@ RM-2P-2S1D: Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2 is in bits 8:9, Rdest1_EXTRA2 in 10:11) +Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2. + Note also that LD with update indexed, which takes 2 src and 2 dest (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also Twin Predication. therefore these are treated as RM-2P-2S1D and the -- 2.30.2