From 98cbcbb54f56475759fae747b60e47568617640f Mon Sep 17 00:00:00 2001 From: Austin Harris Date: Sat, 7 Jul 2018 15:43:27 -0500 Subject: [PATCH] arch-riscv: Fix the srlw and srliw instructions. Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Signed-off-by: Austin Harris Reviewed-on: https://gem5-review.googlesource.com/11669 Reviewed-by: Alec Roelke Maintainer: Alec Roelke --- src/arch/riscv/isa/decoder.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index d8f3395e3..b4bf3854b 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -447,7 +447,7 @@ decode QUADRANT default Unknown::unknown() { }}); 0x5: decode SRTYPE { 0x0: srliw({{ - Rd = Rs1_uw >> SHAMT5; + Rd_sd = (int32_t)(Rs1_uw >> SHAMT5); }}); 0x1: sraiw({{ Rd_sd = Rs1_sw >> SHAMT5; @@ -759,7 +759,7 @@ decode QUADRANT default Unknown::unknown() { }}, IntDivOp); 0x5: decode FUNCT7 { 0x0: srlw({{ - Rd_uw = Rs1_uw >> Rs2<4:0>; + Rd_sd = (int32_t)(Rs1_uw >> Rs2<4:0>); }}); 0x1: divuw({{ if (Rs2_uw == 0) { -- 2.30.2