From 98d1020416298d59cb18975f1a6fa54bc3ae36bc Mon Sep 17 00:00:00 2001 From: "Daniel R. Carvalho" Date: Tue, 6 Oct 2020 12:45:45 +0200 Subject: [PATCH] mem-cache: Isolate prefetching bit Previously the prefetching bit was among the status bits; yet, it has no correlation with the other bits. It has been isolated as a single boolean, with a respective getter and setter. Change-Id: Ibe76e1196ca17a7c9ab9bda2216186707427cb64 Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35699 Reviewed-by: Jason Lowe-Power Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris Tested-by: kokoro --- src/mem/cache/base.cc | 2 +- src/mem/cache/cache.cc | 2 +- src/mem/cache/cache_blk.hh | 20 ++++++++++++++------ src/mem/cache/noncoherent_cache.cc | 2 +- 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index fc2115a2a..7b6b3c38d 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -367,7 +367,7 @@ BaseCache::recvTimingReq(PacketPtr pkt) ppHit->notify(pkt); if (prefetcher && blk && blk->wasPrefetched()) { - blk->status &= ~BlkHWPrefetched; + blk->clearPrefetched(); } handleTimingReqHit(pkt, blk, request_time); diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 8e45ea347..9e87c2ade 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -850,7 +850,7 @@ Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) case MSHR::Target::FromPrefetcher: assert(tgt_pkt->cmd == MemCmd::HardPFReq); if (blk) - blk->status |= BlkHWPrefetched; + blk->setPrefetched(); delete tgt_pkt; break; diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh index b0d45af55..4483fb134 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/cache_blk.hh @@ -69,8 +69,6 @@ enum CacheBlkStatusBits : unsigned { BlkReadable = 0x04, /** dirty (modified) */ BlkDirty = 0x08, - /** block was a hardware prefetch yet unaccessed*/ - BlkHWPrefetched = 0x20, /** block holds compressed data */ BlkCompressed = 0x80 }; @@ -176,6 +174,7 @@ class CacheBlk : public TaggedEntry virtual void invalidate() { TaggedEntry::invalidate(); + clearPrefetched(); setTaskId(ContextSwitchTaskId::Unknown); status = 0; whenReady = MaxTick; @@ -198,10 +197,16 @@ class CacheBlk : public TaggedEntry * be touched. * @return True if the block was a hardware prefetch, unaccesed. */ - bool wasPrefetched() const - { - return (status & BlkHWPrefetched) != 0; - } + bool wasPrefetched() const { return _prefetched; } + + /** + * Clear the prefetching bit. Either because it was recently used, or due + * to the block being invalidated. + */ + void clearPrefetched() { _prefetched = false; } + + /** Marks this blocks as a recently prefetched block. */ + void setPrefetched() { _prefetched = false; } /** * Get tick at which block's data will be available for access. @@ -423,6 +428,9 @@ class CacheBlk : public TaggedEntry * meaningful if the block is valid. */ Tick _tickInserted; + + /** Whether this block is an unaccessed hardware prefetch. */ + bool _prefetched; }; /** diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc index 5ca1da0cf..0cea4945e 100644 --- a/src/mem/cache/noncoherent_cache.cc +++ b/src/mem/cache/noncoherent_cache.cc @@ -288,7 +288,7 @@ NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, assert(tgt_pkt->cmd == MemCmd::HardPFReq); if (blk) - blk->status |= BlkHWPrefetched; + blk->setPrefetched(); // We have filled the block and the prefetcher does not // require responses. -- 2.30.2