From 98e108034561bb3a9276594ebef2f80da38748ad Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 9 Jun 2020 09:56:23 +0000 Subject: [PATCH] flatten: accept processes. --- passes/techmap/flatten.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index a2794541a..a03226f9f 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -79,14 +79,6 @@ struct FlattenWorker void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector &new_cells) { - if (tpl->processes.size() != 0) { - log("Flattening yielded processes:"); - for (auto &it : tpl->processes) - log(" %s",log_id(it.first)); - log("\n"); - log_error("Flattening yielded processes -> this is not supported.\n"); - } - // Copy the contents of the flattened cell dict memory_map; @@ -127,6 +119,14 @@ struct FlattenWorker design->select(module, new_wire); } + for (auto &tpl_proc_it : tpl->processes) { + RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second); + map_attributes(cell, new_proc, tpl_proc_it.second->name); + auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); }; + new_proc->rewrite_sigspecs(rewriter); + design->select(module, new_proc); + } + for (auto tpl_cell : tpl->cells()) { RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell), tpl_cell); map_attributes(cell, new_cell, tpl_cell->name); -- 2.30.2