From 98f680056907689de48a4f63e9e37499764b83ad Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 1 Mar 2020 17:26:36 +0000 Subject: [PATCH] --- openpower.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openpower.mdwn b/openpower.mdwn index e557bab09..fbd1a96db 100644 --- a/openpower.mdwn +++ b/openpower.mdwn @@ -22,6 +22,12 @@ Summary * no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE * needs escape sequencing (ISAMUX/NS) +# What we are *NOT* doing: + +* Opcode 4 Signal Processing (SPE) +* Opcode 4 Vectors +* Avoidable legacy opcodes + # SimpleV see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below. @@ -35,6 +41,10 @@ Thus it is completely unnecessary to add any vector opcodes - at all - saving hugely on both hardware and compiler development time when the concept is dropped on top of a pre-existing ISA. +# Integer Overflow / Saturate + +Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations. + # atomics Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists. -- 2.30.2