From 9916f2d2af18a26f32efb85aff5c11e1b998e19c Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Thu, 17 May 2012 13:05:07 -0400
Subject: [PATCH] radeon/llvm: Remove AMDIL floating-point ADD instruction defs

---
 src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl    | 3 +--
 src/gallium/drivers/radeon/AMDILInstructions.td      | 1 -
 src/gallium/drivers/radeon/R600Instructions.td       | 6 +++---
 src/gallium/drivers/radeon/R600LowerInstructions.cpp | 2 +-
 src/gallium/drivers/radeon/SIInstructions.td         | 5 ++++-
 5 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index a6a76271565..498ef13baee 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -35,7 +35,6 @@ my @F32_MULTICLASSES = qw {
   UnaryIntrinsicFloat
   UnaryIntrinsicFloatScalar
   TernaryIntrinsicFloat
-  BinaryOpMCFloat
 };
 
 my @I32_MULTICLASSES = qw {
@@ -57,7 +56,7 @@ my $FILE_TYPE = $ARGV[0];
 
 open AMDIL, '<', 'AMDILInstructions.td';
 
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'MIN_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'MIN_f32', 'MUL_IEEE_f32');
 
 while (<AMDIL>) {
   if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 5ea541c4d1f..e512e265f5e 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -216,7 +216,6 @@ def LUSHR        : TwoInOneOut<IL_OP_U64_SHR, (outs GPRI64:$dst),
 let hasIEEEFlag = 1 in {
 defm MUL_IEEE  : BinaryOpMCFloat<IL_OP_MUL_IEEE, IL_OP_D_MUL, fmul>;
 }
-defm ADD  : BinaryOpMCFloat<IL_OP_ADD, IL_OP_D_ADD, fadd>;
 //===---------------------------------------------------------------------===//
 // float math instructions start here
 //===---------------------------------------------------------------------===//
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index f7fe34b7326..c66d62d2be3 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -244,9 +244,9 @@ let Gen = AMDGPUGen.R600_CAYMAN  in {
 
 def ADD : R600_2OP <
   0x0, "ADD",
-  [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] > {
-  let AMDILOp = AMDILInst.ADD_f32;
-}
+  [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
+
 // Non-IEEE MUL: 0 * anything = 0
 def MUL : R600_2OP <
   0x1, "MUL NON-IEEE",
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index 5a0f1d9cca9..19c3aae1e61 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -307,7 +307,7 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
         {
           MI.getOperand(2).addTargetFlag(MO_FLAG_NEG);
           BuildMI(MBB, I, MBB.findDebugLoc(I),
-                          TII->get(TII->getISAOpcode(AMDIL::ADD_f32)))
+                          TII->get(TII->getISAOpcode(AMDIL::ADD)))
                   .addOperand(MI.getOperand(0))
                   .addOperand(MI.getOperand(1))
                   .addOperand(MI.getOperand(2));
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 4efc093e374..c1c96999b0e 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -590,7 +590,10 @@ def V_CNDMASK_B32 : VOP2_Helper <
 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>;
 
-defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", [], AMDILInst.ADD_f32>;
+defm V_ADD_F32 : VOP2_32 <
+  0x00000003, "V_ADD_F32",
+  [(set VReg_32:$dst, (fadd AllReg_32:$src0, VReg_32:$src1))]
+>;
 
 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", []>;
 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>;
-- 
2.30.2