From 99190d4378c5d3473011577d468fcbf07ee9e6ed Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 15 May 2023 17:41:11 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 878915662..a7a96e7ba 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -257,15 +257,21 @@ Memory access remains exactly the same: the effects of `MSR.LE` remain exactly the same, affecting as they already do and remain **only** on the Load and Store memory-register operation byte-order, and having nothing to do with the ordering of the contents of register files or -register-register operations. +register-register arithmetic or logical operations. The only major impact on Arithmetic and Logical operations is that all Scalar operations are defined, where practical and workable, to have -three new widths: elwidth=32, elwidth=16, elwidth=8. The default of +three new widths: elwidth=32, elwidth=16, elwidth=8. + +*Architectural note: a future revision of SVP64 for VSX may have entirely +different definitions of possible elwidths.* + +The default of elwidth=64 is the pre-existing (Scalar) behaviour which remains 100% unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit variant of `addi`, but the sole exclusive difference is the width. -*In no way* is the actual `addi` instruction fundamentally altered. +*In no way* is the actual `addi` instruction fundamentally altered +to become an entirely different operation. FP Operations elwidth overrides are also defined, as explained in the [[svp64/appendix]]. @@ -274,7 +280,7 @@ To be absolutely clear: ``` There are no conceptual arithmetic ordering or other changes over the Scalar Power ISA definitions to registers or register files or to - arithmetic or Logical Operations beyond element-width subdivision + arithmetic or Logical Operations, beyond element-width subdivision ``` Element offset -- 2.30.2