From 992454e0f2df37a296ad8e173d613977b84e8703 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 13 Jan 2020 17:00:41 -0800 Subject: [PATCH] fastmodel: Ensure unset vec reg bits are zero/false. These bits won't be overwritten with values from IRIS, and so we should make sure they're cleared and don't have old values or junk. Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24327 Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/fastmodel/iris/thread_context.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index f487ebc7c..f3b4c95af 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -572,12 +572,14 @@ const ArmISA::VecRegContainer & ThreadContext::readVecReg(const RegId ®_id) const { const RegIndex idx = reg_id.index(); + ArmISA::VecRegContainer ® = vecRegs.at(idx); + reg.zero(); + // Ignore accesses to registers which aren't architected. gem5 defines a // few extra registers which it uses internally in the implementation of // some instructions. if (idx >= vecRegIds.size()) - return vecRegs.at(idx); - ArmISA::VecRegContainer ® = vecRegs.at(idx); + return reg; iris::ResourceReadResult result; call().resource_read(_instId, result, vecRegIds.at(idx)); @@ -598,10 +600,12 @@ const ArmISA::VecPredRegContainer & ThreadContext::readVecPredReg(const RegId ®_id) const { RegIndex idx = reg_id.index(); - if (idx >= vecPredRegIds.size()) - return vecPredRegs.at(idx); ArmISA::VecPredRegContainer ® = vecPredRegs.at(idx); + reg.reset(); + + if (idx >= vecPredRegIds.size()) + return reg; iris::ResourceReadResult result; call().resource_read(_instId, result, vecPredRegIds.at(idx)); -- 2.30.2