From 994099bb20f7487fff0ec18b343245cc33191696 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Sat, 22 Aug 1998 00:11:24 +0000 Subject: [PATCH] sparc.md (TFmode splits): Handle destination registers being referenced in the address correctly. * config/sparc/sparc.md (TFmode splits): Handle destination registers being referenced in the address correctly. From-SVN: r21901 --- gcc/ChangeLog | 5 +++++ gcc/config/sparc/sparc.md | 18 ++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0c72f928630..319d3145150 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Fri Aug 21 23:07:46 1998 David S. Miller + + * config/sparc/sparc.md (TFmode splits): Handle destination + registers being referenced in the address correctly. + Fri Aug 21 19:31:31 1998 Alexandre Petit-Bianco * tree.def (LABELED_BLOCK_EXPR, EXIT_BLOCK_EXPR): New tree nodes. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 365d1638f5d..9796ec794de 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -3333,12 +3333,26 @@ rtx word1 = change_address (operands[1], DFmode, plus_constant_for_output (XEXP (word0, 0), 8)); rtx dest1, dest2; + int self_reference = reg_mentioned_p (operands[0], + XEXP (XEXP (word1, 0), 0)); /* Ugly, but gen_highpart will crap out here for 32-bit targets. */ dest1 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN == 0); dest2 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN != 0); - emit_insn (gen_movdf (dest1, word0)); - emit_insn (gen_movdf (dest2, word1)); + + /* Now output, ordering such that we don't clobber any registers + mentioned in the address. */ + if (self_reference != 0 + && WORDS_BIG_ENDIAN) + { + emit_insn (gen_movdf (dest2, word1)); + emit_insn (gen_movdf (dest1, word0)); + } + else + { + emit_insn (gen_movdf (dest1, word0)); + emit_insn (gen_movdf (dest2, word1)); + } DONE; }") -- 2.30.2