From 994e1cf73fb769047f7fa1c50f6e6ad1c32abcd7 Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 3 Aug 2020 18:03:26 +0200
Subject: [PATCH] Add more sel tests

---
 gram/test/test_frontend_wishbone.py | 98 ++++++++++++++++++++---------
 1 file changed, 68 insertions(+), 30 deletions(-)

diff --git a/gram/test/test_frontend_wishbone.py b/gram/test/test_frontend_wishbone.py
index 865e74a..27e83e9 100644
--- a/gram/test/test_frontend_wishbone.py
+++ b/gram/test/test_frontend_wishbone.py
@@ -21,7 +21,7 @@ class FakeGramCore:
         self.size = 2**3*128//8
 
 class GramWishboneTestCase(FHDLTestCase):
-    def read_request(self, *, bus, native_port, adr, sel, reference_value, timeout=128):
+    def read_request(self, *, bus, native_port, adr, sel, reference_value, timeout=128, ackCallback=None):
         # Send a read request
         yield bus.adr.eq(adr)
         yield bus.stb.eq(1)
@@ -44,6 +44,8 @@ class GramWishboneTestCase(FHDLTestCase):
             yield
             self.assertTrue(timeout > 0)
 
+        if ackCallback is not None:
+            yield from ackCallback(bus, native_port)
         res = yield bus.dat_r
 
         yield bus.stb.eq(0)
@@ -53,7 +55,7 @@ class GramWishboneTestCase(FHDLTestCase):
 
         return res
 
-    def write_request(self, *, bus, native_port, adr, sel, value, timeout=128):
+    def write_request(self, *, bus, native_port, adr, sel, value, timeout=128, ackCallback=None):
         # Send a write request
         yield bus.adr.eq(adr)
         yield bus.stb.eq(1)
@@ -75,6 +77,8 @@ class GramWishboneTestCase(FHDLTestCase):
             yield
             self.assertTrue(timeout > 0)
 
+        if ackCallback is not None:
+            yield from ackCallback(bus, native_port)
         res = yield native_port.wdata.data
 
         yield bus.stb.eq(0)
@@ -201,7 +205,7 @@ class GramWishboneTestCase(FHDLTestCase):
     def test_write64_64(self):
         self.write_test(data_width=64, granularity=64)
 
-    def test_sel(self):
+    def test_sel_write(self):
         core = FakeGramCore()
         native_port = core.crossbar.get_native_port()
         dut = gramWishbone(core, data_width=32, granularity=8)
@@ -212,33 +216,67 @@ class GramWishboneTestCase(FHDLTestCase):
             yield native_port.wdata.ready.eq(0)
             yield native_port.rdata.valid.eq(0)
 
-            # Send a write request
-            yield dut.bus.adr.eq(0)
-            yield dut.bus.stb.eq(1)
-            yield dut.bus.cyc.eq(1)
-            yield dut.bus.sel.eq(1)
-            yield dut.bus.we.eq(1)
-            yield dut.bus.dat_w.eq(0xA8)
-            yield
-
-            # Answer cmd
-            yield native_port.cmd.ready.eq(1)
-            yield
-
-            # Answer wdata
-            yield native_port.wdata.ready.eq(1)
-
-            timeout = 128
-            while not (yield dut.bus.ack):
-                timeout -= 1
-                yield
-                self.assertTrue(timeout > 0)
-
-            self.assertEqual((yield native_port.wdata.we), 1)
+            reference_value = 0xBADDCAFE_FEEDFACE_BEEFCAFE_BAD0DAB0
 
-            yield dut.bus.stb.eq(0)
-            yield dut.bus.cyc.eq(0)
-            yield dut.native_port.wdata.ready.eq(0)
-            yield
+            def sel1(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0b1)
+            def sel2(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0b10)
+            def sel3(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0b100)
+            def sel4(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0b1000)
+            def sel5(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0b10000)
+            def sel9(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0b100000000)
+
+            yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=0,
+                sel=1,
+                value=0xCA,
+                timeout=128,
+                ackCallback=sel1)
+
+            yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=0,
+                sel=0b10,
+                value=0xCA,
+                timeout=128,
+                ackCallback=sel2)
+
+            yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=0,
+                sel=0b100,
+                value=0xCA,
+                timeout=128,
+                ackCallback=sel3)
+
+            yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=0,
+                sel=0b1000,
+                value=0xCA,
+                timeout=128,
+                ackCallback=sel4)
+
+            yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=1,
+                sel=1,
+                value=0xCA,
+                timeout=128,
+                ackCallback=sel5)
+
+        yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=2,
+                sel=1,
+                value=0xCA,
+                timeout=128,
+                ackCallback=sel9)
 
         runSimulation(dut, process, "test_frontend_wishbone.vcd")
-- 
2.30.2