From 99586fc463c3a0932ae9ca3ac7c2f23a5b5e8c39 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 23 Jan 2021 19:33:44 -0300 Subject: [PATCH] Convert add and sub to return PartitionedSignal Adjust the test suite accordingly. --- src/ieee754/part/partsig.py | 8 ++++++-- src/ieee754/part/test/test_partsig.py | 6 +++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py index 9e6e78b6..f09b972a 100644 --- a/src/ieee754/part/partsig.py +++ b/src/ieee754/part/partsig.py @@ -163,7 +163,9 @@ class PartitionedSignal: comb += pa.a.eq(op1) comb += pa.b.eq(op2) comb += pa.carry_in.eq(carry) - return (pa.output, pa.carry_out) + result = PartitionedSignal.like(self) + comb += result.sig.eq(pa.output) + return result, pa.carry_out def sub_op(self, op1, op2, carry=~0): op1 = getsig(op1) @@ -174,7 +176,9 @@ class PartitionedSignal: comb += pa.a.eq(op1) comb += pa.b.eq(~op2) comb += pa.carry_in.eq(carry) - return (pa.output, pa.carry_out) + result = PartitionedSignal.like(self) + comb += result.sig.eq(pa.output) + return result, pa.carry_out def __add__(self, other): result, _ = self.add_op(self, other, carry=0) diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index 7d87ecee..2bf0ef83 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -149,15 +149,15 @@ class TestAddMod(Elaboratable): # add add_out, add_carry = self.a.add_op(self.a, self.b, self.carry_in) - comb += self.add_output.eq(add_out) + comb += self.add_output.eq(add_out.sig) comb += self.add_carry_out.eq(add_carry) # sub sub_out, sub_carry = self.a.sub_op(self.a, self.b, self.carry_in) - comb += self.sub_output.eq(sub_out) + comb += self.sub_output.eq(sub_out.sig) comb += self.sub_carry_out.eq(sub_carry) # neg - comb += self.neg_output.eq(-self.a) + comb += self.neg_output.eq((-self.a).sig) # left shift comb += self.ls_output.eq(self.a << self.b) # right shift -- 2.30.2